Synthesis problem with noelv-generic

Hello, I’m trying to synthesize the composant NOELVCORE with Synopsys Design Vision N-2017.09 with the help of the the command make dc (or the file compile.dc for the command to use in Synopsis). All the analyze command worked, but the elaborate command did not. This the elaborate command I used :

elaborate NOELVCORE -architecture RTL -library WORK

From this command I have 1 error :

Error: ./…/…/lib/gaisler/noelv/core/cctrlnv.vhd:1528: Internal assertion failure. (VER-37)
*** Presto compilation terminated with 1 errors. ***

The line pointed by the error message is the declaration of the process comb for the component cctrlnv. I do not understand the error message and how I can remove it. I have the same problem if I try the make dc command with the other noelv designs. Could you help me remove this error, or prevent it from interfering with the synthesis ?

At the end of the command elaborate, I have two unresolved references for the design noelvcore, one for cctrlnv which has an error (so I think is normal), and the order is this one :

Warning: Cannot find the design ‘tap_gen’ in the library ‘WORK’. (LBR-1)

I did not find the declaration of this component in the grlib librairie, just the port map and the definition of the component in the package alltap. I don’t know if it’s normal or if it did not influence the result.

For my work, I must not have black boxe in the design, so have you any Idea on how to remove this error ?

Thanks in advance for your answers,

Hello Mehdy,

we are aware that DC has problems with some code in the NOEL-V but unfortunately we did not have time to fix this for this release. If you could let me know which configuration you are interesting in synthesizing with Synopsys DC I may be able to provide some patches when I’m back from vacation in two weeks.

Teh tap_gen is the RTL implementation of the JTAG tap which is not included in the GPL version of GRLIB. If you remove the AHBJTAG for the design, a JTAG tap is not used.


Thank you for your answer,

I’m trying to synthesize the NOELVCORE design with the following configuration : a single-issue GPP64 with the nanofpu and no L2 cache, in other words the General-purpose-cfg(single-issue) with RV64 in the xconfig application.

Thank you again, I will try to resolve my issue with the tap_gen while waiting for your answer for the synthesize,

Best regards,


Please update the file "GRLIB/lib/gaisler/noelv/core/cctrlnv.vhd with the following patch. With this patch, we have been able to synthesize the NOEL-V with Synopsys DC. The patch hardcodes the MMU page table format to Sv39. We may have used a different version of the tool, so please let me know if the patch works or not for you.


--- cctrlnv.vhd	2021-08-13 11:58:30.695287084 +0200
+++ cctrlnv.vhd	2021-08-13 11:59:29.291327994 +0200
@@ -295,7 +295,8 @@
     return gaisler.mmucacheconfig.va_size(riscv_mmu);
-  constant va_size : gaisler.mmucacheconfig.va_bits := va_size_tmp;
+  --constant va_size : gaisler.mmucacheconfig.va_bits := va_size_tmp;
+  constant va_size : gaisler.mmucacheconfig.va_bits(1 to 3) := (9, 9, 9);
   function is_pt_invalid(data : std_logic_vector) return boolean is

Thank you for your answer, it did solve the problem on the file GRLIB/lib/gaisler/noelv/core/cctrlnv.vhd. After that, I have a new error appearing :

Error: ./…/…/lib/gaisler/noelv/core/utilnv.vhd:758: Internal assertion failure. (VER-37)

I can resolve it by commenting the line 758, 759, 760 and 762 of the file GRLIB/lib/gaisler/noelv/core/utilnv.vhd. I don’t know if it’s normal, but with that I do not have error in simulation or in synthesize.

Best regards,

Thank you for reporting the new issue. We have not seen this issue probably because we have used a different version of the tool.

Good that you manage to synthesize the design. We will try fixing these issues for the next release.