Noel-V Arty A7 35T problems

I have just synthesized Noel-V for Arty A7 35T, but when I try to implement it, I get this error:
[5:12 PM] Paul-Cristian Banu-Țăran

[DRC UTLZ-1] Resource utilization: Slice LUTs over-utilized in Top Level Design (This design requires more Slice LUTs cells than are available in the target device. This design requires 59947 of such cell types but only 20800 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter “drc.disableLUTOverUtilError” to 1 to change this error to warning.)

I suppose that the FPGA is too weak. Even though, Noel-V should be usable for Arty A7, even for the old one, 35T. I guess that I have to get rid of some components, but what should I discard from the makefile? Could anybody help me in order to surpass this issue?

Hi Paul,

Are you using the design for Arty A7 on the GPL release of GRLIB as is, or did you add any other IP?

That design has several debug links instantiated by default, namely JTAG, UART and Ethernet. The biggest impact will be to disable Ethernet and the other link you are not using, and stick with either UART or JTAG. The Xilinx memory controller is also quite large, so if you are not using too much RAM, you could replace it with on-chip RAM (ahbram).


Hi Joaquin,

Thanks for the suggestion. I didn’t add any other IP core. I used just those provided within the GRLIB. I would discard those unnecessary components from the build, but I don’t know how. Also, I would like to add a couple of simple peripherals to the design (i.e., to turn on/off an LED whenever a slide switch is positioned in on/off place). And, tbh, I don’t know how to do this either (I am a beginner in Vivado and Noel-V).


Hi Paul,

My first suggestion would be to start removing IPs until the design fits. Only then I advise you to add your IPs.

For removing IPs, you have two options: either via the graphical interface, by typing “make xconfig” from the design directory, or just modifying the design configuration file, config.vhd. I would go for the second option, as it is usually quicker. Please open that file and modify the following lines:

– Gaisler Ethernet core
constant CFG_GRETH : integer := 0; – instead of 1

constant CFG_AHB_UART : integer := 0; – instead of 1

This will still allow you to debug the design with the JTAG debug link. If you prefer to use the UART, disable JTAG instead. It is possible that Vivado throws an error when building the design. If that is the case, it is most likely that you need to remove the constraints for Ethernet, but hopefully you don’t need to do that. Let us know if that is the case.

If this still does not fit in the FPGA, I would suggest to reconfigure the NOEL-V core to have a less performance set-up. We can follow-up on that if necessary.

To add new IPs to the design, I recommend you have a look at the documentation, in particular grlib.pdf, where you can find a section dedicated to adding new IPs to an AMBA system.