NOEL-V/ IP MIG 7 Series on ARTY-A7


I´m trying synthesis the project “noelv-digilent-arty-a7” but I get a error because the difference of MIG 7 IP. The original version in the grlib is from Vivado 2018.1 (4.1), but the recent Vivado versions use the 4.2 MIG version.
When I try Update IP, I get a error and I can´t continue.
Before I only run “make vivado-launch”.

I need install the version 2018.1 to can use this IP and generate again the bitfile for the board?


Hi Marte,

I have tried to synthesize the noelv-digilent-arty-a7 design with Vivado 2022.2 and it worked - I got bitfiles and the design could meet timing. The steps I followed:

  1. Launch make vivado-launch
  2. Click on IP sources, right click on mig and select “Upgrade IP”.
  3. Repeat the previous step for mig_cdc.
  4. I tend not to synthesize the Vivado IPs out-of-context, so I will normally skip those steps and synthesize all together.
  5. Run the implementation.

Let us know if this solves the issue. Otherwise please indicate which specific version of Vivado you are using.