I´m trying synthesis the project “noelv-digilent-arty-a7” but I get a error because the difference of MIG 7 IP. The original version in the grlib is from Vivado 2018.1 (4.1), but the recent Vivado versions use the 4.2 MIG version.
When I try Update IP, I get a error and I can´t continue.
Before I only run “make vivado-launch”.
I need install the version 2018.1 to can use this IP and generate again the bitfile for the board?