Error compiling NOEL-V with Modelsim

Hello,
I am coming back to grlib after several years to try NOEL-V, but I cannot get it to work. Here are my steps:

  • I go to ./design/noelv-xilinx-vc707
  • Following README, I first issue “make map_xilinx_7series_lib” compilation is fine with no error
  • I then try “make sim” and I get this error:
    vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/unisim/memory_ultrascale.vhd
    ** Error: (vcom-11) Could not find unisim.vcomponents.
…/…/lib/techmap/unisim/memory_ultrascale.vhd(33): use UNISIM.vcomponents.all;

** Error (suppressible): …/…/lib/techmap/unisim/memory_ultrascale.vhd(33): (vcom-1195) Cannot find expanded name “unisim.vcomponents”.
** Error: …/…/lib/techmap/unisim/memory_ultrascale.vhd(33): Unknown expanded name.

…/…/lib/techmap/unisim/memory_ultrascale.vhd(38): entity ultrascale_syncram is

** Error: …/…/lib/techmap/unisim/memory_ultrascale.vhd(38): VHDL Compiler exiting
make[2]: *** [vsim] Error 2
make[2]: Leaving directory /calcul/gailser/grlib-gpl-2020.4-b4261/designs/noelv-xilinx-vc707' make[1]: *** [make.work] Error 2 make[1]: Leaving directory /calcul/gailser/grlib-gpl-2020.4-b4261/designs/noelv-xilinx-vc707’
make: *** [sim] Error 2

I am using modelsim 10.4 and Vivado 2018.1

I tried to use compiling from another noel-V design and I get the same error. Any ideas?

It seems the unisim library needs to be created and compiled from your Vivado. The source files are here for my Vivado 2020.1:

C:\Xilinx\Vivado\2020.1\data\vhdl\src

Not sure if the script compiles those for you or you have to manually do that step.

Hi,

I can’t reproduce the error at my end. map_xilinx_7series_lib uses Vivado to compile the Xilinx libraries - among others the unisim library - and maps them in modelsim.ini, so that the simulator can find them. The libraries are compiled to ./xilinx_lib/ so you should be able to find a unisim directory there. Can you please post the output from map_xilinx_7series_lib, so that we can check them.

Best regards,
Martin

Hi, here is the output I get starting after a distclean:

xph2slempo@cimepe36:/calcul/gailser/grlib-gpl-2020.4-b4261/designs/noelv-xilinx-vc707$ make map_xilinx_7series_lib
GRLIB settings:
GRLIB = …/…
GRLIB_CONFIG = noelv_config.vhd
GRLIB_SIMULATOR = ModelSim
TECHLIBS setting = unisim
Top-level design = noelvmp
Simulation top-level = testbench
Scanning libraries:
grlib: stdlib util sparc riscv modgen amba dftlib
techmap: gencomp alltech inferred unisim maps
eth: comp core wrapper
opencores: can i2c ge_1000baseX
gaisler: arith memctrl srmmu leon3 leon3v3 leon4 l2cache/pkg can axi misc net uart sim jtag greth usb ddr i2c spi subsys noelv pl ic noelv/subsys leon5 leon5v0
work: debug

****** Vivado v2018.1 (64-bit)
**** SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018
**** IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source ./xilinx_lib/noelvmp_simlib.tcl

compile_simlib -quiet -directory ./xilinx_lib/ -family all -language all -simulator modelsim -library unisim -library simprim

INFO: [Common 17-206] Exiting Vivado at Wed Feb 3 16:02:19 2021…
Model Technology ModelSim SE-64 vmap 10.4 Lib Mapping Utility 2014.12 Dec 2 2014
vmap secureip_ver ./xilinx_lib/secureip
Modifying modelsim.ini
Model Technology ModelSim SE-64 vmap 10.4 Lib Mapping Utility 2014.12 Dec 2 2014
vmap secureip ./xilinx_lib/secureip
Modifying modelsim.ini
Model Technology ModelSim SE-64 vmap 10.4 Lib Mapping Utility 2014.12 Dec 2 2014
vmap axi_bfm ./xilinx_lib/secureip
Modifying modelsim.ini
Model Technology ModelSim SE-64 vmap 10.4 Lib Mapping Utility 2014.12 Dec 2 2014
vmap unisims_ver ./xilinx_lib/unisims_ver
Modifying modelsim.ini
Model Technology ModelSim SE-64 vmap 10.4 Lib Mapping Utility 2014.12 Dec 2 2014
vmap unisim ./xilinx_lib/unisim
Modifying modelsim.ini
Model Technology ModelSim SE-64 vmap 10.4 Lib Mapping Utility 2014.12 Dec 2 2014
vmap unimacro_ver ./xilinx_lib/unimacro_ver
Modifying modelsim.ini
Model Technology ModelSim SE-64 vmap 10.4 Lib Mapping Utility 2014.12 Dec 2 2014
vmap unimacro ./xilinx_lib/unimacro
Modifying modelsim.ini
Model Technology ModelSim SE-64 vmap 10.4 Lib Mapping Utility 2014.12 Dec 2 2014
vmap simprim_ver ./xilinx_lib/simprims_ver
Modifying modelsim.ini
Model Technology ModelSim SE-64 vmap 10.4 Lib Mapping Utility 2014.12 Dec 2 2014
vmap unifast_ver ./xilinx_lib/unifast_ver
Modifying modelsim.ini
Model Technology ModelSim SE-64 vmap 10.4 Lib Mapping Utility 2014.12 Dec 2 2014
vmap unifast ./xilinx_lib/unifast_ver
Modifying modelsim.ini

xph2slempo@cimepe36:/calcul/gailser/grlib-gpl-2020.4-b4261/designs/noelv-xilinx-vc707$ make sim
make vsim
make[1]: Entering directory `/calcul/gailser/grlib-gpl-2020.4-b4261/designs/noelv-xilinx-vc707’
Reading pref.tcl

10.4

do libs.do

quit

make[2]: Entering directory `/calcul/gailser/grlib-gpl-2020.4-b4261/designs/noelv-xilinx-vc707’
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/stdlib/version.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/stdlib/config_types.vhd
vcom -quiet -explicit -O0 -93 -work grlib noelv_config.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/stdlib/stdlib.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/stdlib/stdio.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/stdlib/testlib.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/util/util.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/sparc/sparc.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/sparc/sparc_disas.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/sparc/cpu_disas.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/riscv/riscv.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/riscv/riscv_disas.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/riscv/cpu_disas.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/modgen/multlib.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/modgen/leaves.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/amba.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/devices.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/defmst.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/apbctrl.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/apbctrlx.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/apbctrldp.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/apbctrlsp.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/ahbctrl.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/dma2ahb_pkg.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/dma2ahb.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/ahbmst.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/ahblitm2ahbm.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/dma2ahb_tp.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/amba_tp.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/dftlib/dftlib.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/dftlib/trstmux.vhd
vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/dftlib/synciotest.vhd
vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/gencomp/gencomp.vhd
vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/gencomp/netcomp.vhd
vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/alltech/allclkgen.vhd
vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/alltech/allddr.vhd
vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/alltech/allmem.vhd
vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/alltech/allmul.vhd
vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/alltech/allpads.vhd
vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/alltech/alltap.vhd
vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/inferred/memory_inferred.vhd
vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/inferred/ddr_inferred.vhd
vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/inferred/mul_inferred.vhd
vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/inferred/ddr_phy_inferred.vhd
vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/inferred/ddrphy_datapath.vhd
vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/inferred/fifo_inferred.vhd
vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/inferred/sim_pll.vhd
vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/inferred/lpddr2_phy_inferred.vhd
vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/unisim/memory_kintex7.vhd
vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/unisim/memory_ultrascale.vhd
** Error: (vcom-11) Could not find unisim.vcomponents.

…/…/lib/techmap/unisim/memory_ultrascale.vhd(33): use UNISIM.vcomponents.all;

** Error (suppressible): …/…/lib/techmap/unisim/memory_ultrascale.vhd(33): (vcom-1195) Cannot find expanded name “unisim.vcomponents”.
** Error: …/…/lib/techmap/unisim/memory_ultrascale.vhd(33): Unknown expanded name.

…/…/lib/techmap/unisim/memory_ultrascale.vhd(38): entity ultrascale_syncram is

** Error: …/…/lib/techmap/unisim/memory_ultrascale.vhd(38): VHDL Compiler exiting
make[2]: *** [vsim] Error 2
make[2]: Leaving directory /calcul/gailser/grlib-gpl-2020.4-b4261/designs/noelv-xilinx-vc707' make[1]: *** [make.work] Error 2 make[1]: Leaving directory /calcul/gailser

I tried compiling manually vcomponents:
vcom /softslin/vivado_18.1/Vivado/2018.1/data/vhdl/src/unisims/unisim_VCOMP.vhd -work unisim
Bit it just shifts the issue: after it still cannot find the RAMBxx components inside VCOMP

Regards,
Michele

Hi Michele,

Thank you! I now realized I used another version of Modelsim than you and when I switch to Modelsim 10.4 I get the same error. Do you have access to a newer version of Modelsim? I tried with 10.6a without getting an error.

Best regards,
Martin

The script used for compiling the Xilinx libraries have the -quiet flag set, which removes most of the output. If one mimics what the script environment does without the quiet flag, Vivado gives the following warning:

WARNING: [Vivado 12-5495] Detected incompatible modelsim simulator installation version ‘10.4’! The supported simulator version for the current Vivado release is ‘10.6c’.

The release notes of Vivado 2018.1 lists Modelsim 10.6c as the compatible version, so it’s possible that something doesn’t work as expected when compiling for 10.4, but since the libraries are created by Vivado, the GRLIB script environment doesn’t detect the incompatibility.

Best regards,
Martin

I did not know about this incompatibility, thanks for finding out!
The more recent version we have is 10.5 and it is still incompatible, I will ask for a newer version to be installed.
BTW, is there a possibility to simulate the Noel-V using only generic technology to remove dependency to unisim?

Thanks,

Michele

NOEL-V is possible to simulate without technology dependencies, but the current NOEL-V template designs target Xilinx FPGAs.

Best regards,
Martin

I have been trying all combinations of tools, I cannot get it to work.

  • my admin installed 10.6.c, but is Questasim, not Modelsim. Apparently it changed denomination after 10.5
  • I can get the simulation to start, but I immediately get an “IU in Error Mode”.
  • I followed all steps, cannot really understand what I am doing wrong.

Quite a pity there is not a simple “generic” testbench just for simulation. It was one of the strong points of all Leon2: you could get it up and running really fast and then start minding about FPGA…

I took detailed logs of all the steps, I put them on a file sender to avoid clogging up the forum.

Compilation and Simulation logs

Any idea where it gets wrong?

Thanks,
Michele

Hi Michele,

We will try to update the NOEL-V template designs to make them easier to simulate for the next GRLIB release. In the mean time, I have prepared a simple generic NOEL-V template design which should be easy to simulate in GRLIB. Please download the noelv-generic (http://gaisler.com/tmp/noelv-generic.tar.gz) template design and place it in the GRLIB/designs directory.

I hope this can get you started trying out our NOEL-V processor.

Regards,
Nils

Thank you very much, it works perfectly!

Best regards,

Micheme