Hello,
I am a new user to GRLIB. I am trying to generate a Leon3 core for the ZCU102 (Zynq Ultrascale+ MPSoC).There are no example designs for this board, so I am trying to use the ‘leon3mp’ example as my starting point, and will map the technology to inferred.
I am using GRLIB version grlib-gpl-2021.1-b4265.
I am running bash shell on RH release 7.9.
I am using the following tools:
Vivado 2020.1
Questa 2019.4_1
Following the instructions in ‘grlib.pdf’, Section 2.5, I set the following:
export GRLIB=“/mypath/gaisler_grlib/grlib-gpl-2021.1-b4265”
export XILINX=“/mypath/tools/xilinx/2020.1/Vivado/2020.1/data”
Then do the following (NOTE: I must specify Questa or I get an error):
cd grlib-gpl-2021.1-b4265
make map_xilinx_7series_lib GRLIB_SIMULATOR=“Questa”
cd designs/leon3mp
make sim GRLIB_SIMULATOR=“Questa”
I get the following errors:
** Error: (vcom-11) Could not find unisim.vcomponents.
…/…/lib/techmap/unisim/memory_ultrascale.vhd(33): use UNISIM.vcomponents.all;
** Error (suppressible): …/…/lib/techmap/unisim/memory_ultrascale.vhd(33): (vcom-1195) Cannot find expanded name “unisim.vcomponents”.
** Error: …/…/lib/techmap/unisim/memory_ultrascale.vhd(33): Unknown expanded name.…/…/lib/techmap/unisim/memory_ultrascale.vhd(38): entity ultrascale_syncram is
** Note: …/…/lib/techmap/unisim/memory_ultrascale.vhd(38): VHDL Compiler exiting
make[2]: *** [vsim] Error 2
I next try the following:
cd grlib-gpl-2021.1-b4265
make clean
make install-unisim
make map_xilinx_7series_lib GRLIB_SIMULATOR=“Questa”
cd designs/leon3mp
make clean
make sim GRLIB_SIMULATOR=“Questa”
I get the following errors:
- Error: (vcom-11) Could not find unisim.ramb16_s36_s36.
…/…/lib/techmap/unisim/memory_unisim.vhd(36): use unisim.RAMB16_S36_S36;
** Error (suppressible): …/…/lib/techmap/unisim/memory_unisim.vhd(36): (vcom-1195) Cannot find expanded name “unisim.RAMB16_S36_S36”.
** Error: (vcom-11) Could not find unisim.ramb16_s36.…/…/lib/techmap/unisim/memory_unisim.vhd(37): use unisim.RAMB16_S36;
** Error (suppressible): …/…/lib/techmap/unisim/memory_unisim.vhd(37): (vcom-1195) Cannot find expanded name “unisim.RAMB16_S36”.
** Error: (vcom-11) Could not find unisim.ramb16_s18.
etc…
I also tried other options, such as:
cd grlib-gpl-2021.1-b4265
make clean
make install-unisim
make map_xilinx_7series_lib GRLIB_SIMULATOR=“Questa”
cd designs/leon3mp
make clean
make sim GRLIB_SIMULATOR=“Questa” SKIP_SIM_TECHLIBS=“1”
I get the following errors:
…/…/lib/techmap/unisim/memory_ultrascale.vhd(32): library unisim;
** Error: …/…/lib/techmap/unisim/memory_ultrascale.vhd(32): (vcom-1598) Library “unisim” not found.
…/…/lib/techmap/unisim/memory_ultrascale.vhd(33): use UNISIM.vcomponents.all;
** Error: …/…/lib/techmap/unisim/memory_ultrascale.vhd(33): (vcom-1136) Unknown identifier “UNISIM”.
…/…/lib/techmap/unisim/memory_ultrascale.vhd(38): entity ultrascale_syncram is
** Note: …/…/lib/techmap/unisim/memory_ultrascale.vhd(38): VHDL Compiler exiting
Finally if I do this:
cd grlib-gpl-2021.1-b4265
make clean
make map_xilinx_7series_lib GRLIB_SIMULATOR="Questa"
cd designs/leon3mp
make clean
make sim GRLIB_SIMULATOR="Questa" TECHLIBS="inferred"
make sim-launch
The compile works successfully, and I am able to run the default simulation.
However, I’m concerned about this workaround. Is specifying TECHLIBS=inferred okay,
or am I setting myself up for later problems? Why was this necessary?
For example, I was able to run Vivado P&R (after fixing the targeted device type):
make vivado-launch
However I found that if I changed the JTAG Debug Link setting to yes (in xconfig),
I get this error in Vivado:
[DRC INBB-3] Black Box Instances: Cell ‘ahbjtaggen0.ahbjtag0/tap0/inf.u0’ of type ‘tap_gen’ has undefined contents and is considered a black box.
The contents of this cell must be defined for opt_design to complete successfully.
I found the component for ‘tap_gen’ here:
grlib-gpl-2021.1-b4265/lib/techmap/alltech/alltap.vhd
But I cannot find the entity/architecture for ‘tap_gen’ in the GRLIB.
I don’t think this problem is related to me using TECHLIBS=inferred, but this is my concern, that I do not have my libraries compiled properly. Is the ‘tap_gen’ issue a completely separate problem?
This appears similar to another topic (Error compiling NOEL-V with Modelsim), and the resolution sounded like it required a patch to the GRLIB to fix it. Perhaps that is the same for this issue?
Thanks for any support on this.