Error compiling Leon3 with Questa for Ultrascale+

Hello,

I am a new user to GRLIB. I am trying to generate a Leon3 core for the ZCU102 (Zynq Ultrascale+ MPSoC).There are no example designs for this board, so I am trying to use the ‘leon3mp’ example as my starting point, and will map the technology to inferred.

I am using GRLIB version grlib-gpl-2021.1-b4265.
I am running bash shell on RH release 7.9.
I am using the following tools:

 Vivado 2020.1
 Questa 2019.4_1  

Following the instructions in ‘grlib.pdf’, Section 2.5, I set the following:

export GRLIB="/mypath/gaisler_grlib/grlib-gpl-2021.1-b4265"
export XILINX="/mypath/tools/xilinx/2020.1/Vivado/2020.1/data"

Then do the following (NOTE: I must specify Questa or I get an error):
cd grlib-gpl-2021.1-b4265
make map_xilinx_7series_lib GRLIB_SIMULATOR=“Questa”
cd designs/leon3mp
make sim GRLIB_SIMULATOR=“Questa”

I get the following errors:

** Error: (vcom-11) Could not find unisim.vcomponents.

…/…/lib/techmap/unisim/memory_ultrascale.vhd(33): use UNISIM.vcomponents.all;

** Error (suppressible): …/…/lib/techmap/unisim/memory_ultrascale.vhd(33): (vcom-1195) Cannot find expanded name “unisim.vcomponents”.
** Error: …/…/lib/techmap/unisim/memory_ultrascale.vhd(33): Unknown expanded name.

…/…/lib/techmap/unisim/memory_ultrascale.vhd(38): entity ultrascale_syncram is

** Note: …/…/lib/techmap/unisim/memory_ultrascale.vhd(38): VHDL Compiler exiting
make[2]: *** [vsim] Error 2

I next try the following:

cd grlib-gpl-2021.1-b4265
make clean
make install-unisim
make map_xilinx_7series_lib GRLIB_SIMULATOR=“Questa”
cd designs/leon3mp
make clean
make sim GRLIB_SIMULATOR=“Questa”

I get the following errors:

  • Error: (vcom-11) Could not find unisim.ramb16_s36_s36.
…/…/lib/techmap/unisim/memory_unisim.vhd(36): use unisim.RAMB16_S36_S36;

** Error (suppressible): …/…/lib/techmap/unisim/memory_unisim.vhd(36): (vcom-1195) Cannot find expanded name “unisim.RAMB16_S36_S36”.
** Error: (vcom-11) Could not find unisim.ramb16_s36.

…/…/lib/techmap/unisim/memory_unisim.vhd(37): use unisim.RAMB16_S36;

** Error (suppressible): …/…/lib/techmap/unisim/memory_unisim.vhd(37): (vcom-1195) Cannot find expanded name “unisim.RAMB16_S36”.
** Error: (vcom-11) Could not find unisim.ramb16_s18.
etc…

I also tried other options, such as:

cd grlib-gpl-2021.1-b4265
make clean
make install-unisim
make map_xilinx_7series_lib GRLIB_SIMULATOR=“Questa”
cd designs/leon3mp
make clean
make sim GRLIB_SIMULATOR=“Questa” SKIP_SIM_TECHLIBS=“1”

I get the following errors:

…/…/lib/techmap/unisim/memory_ultrascale.vhd(32): library unisim;

** Error: …/…/lib/techmap/unisim/memory_ultrascale.vhd(32): (vcom-1598) Library “unisim” not found.

…/…/lib/techmap/unisim/memory_ultrascale.vhd(33): use UNISIM.vcomponents.all;

** Error: …/…/lib/techmap/unisim/memory_ultrascale.vhd(33): (vcom-1136) Unknown identifier “UNISIM”.

…/…/lib/techmap/unisim/memory_ultrascale.vhd(38): entity ultrascale_syncram is

** Note: …/…/lib/techmap/unisim/memory_ultrascale.vhd(38): VHDL Compiler exiting

Finally if I do this:

cd grlib-gpl-2021.1-b4265 
make clean
make map_xilinx_7series_lib GRLIB_SIMULATOR="Questa" 
cd designs/leon3mp
make clean
make sim GRLIB_SIMULATOR="Questa" TECHLIBS="inferred" 
make sim-launch

The compile works successfully, and I am able to run the default simulation.
However, I’m concerned about this workaround. Is specifying TECHLIBS=inferred okay,
or am I setting myself up for later problems? Why was this necessary?

For example, I was able to run Vivado P&R (after fixing the targeted device type):
make vivado-launch

However I found that if I changed the JTAG Debug Link setting to yes (in xconfig),
I get this error in Vivado:

[DRC INBB-3] Black Box Instances: Cell ‘ahbjtaggen0.ahbjtag0/tap0/inf.u0’ of type ‘tap_gen’ has undefined contents and is considered a black box.
The contents of this cell must be defined for opt_design to complete successfully.

I found the component for ‘tap_gen’ here:
grlib-gpl-2021.1-b4265/lib/techmap/alltech/alltap.vhd

But I cannot find the entity/architecture for ‘tap_gen’ in the GRLIB.

I don’t think this problem is related to me using TECHLIBS=inferred, but this is my concern, that I do not have my libraries compiled properly. Is the ‘tap_gen’ issue a completely separate problem?

This appears similar to another topic (Error compiling NOEL-V with Modelsim), and the resolution sounded like it required a patch to the GRLIB to fix it. Perhaps that is the same for this issue?

Thanks for any support on this.

Hi,

It should be sufficient to run make map_xilinx_7series_lib for Ultrascale+ devices. make install-unisim is intended for devices using ISE and will copy the simulation models from the Xilinx tool.

Make sure your version of Questasim and Vivado are compatible. If the Questasim version isn’t supported by the Vivado version, the simulation libraries aren’t compiled. The GRLIB script enviroment will automatically add the -quiet flag to the compilation, thereby suppressing any errors from Vivado during the compilation of the simulation libraries.

Best regards,
Martin

Martin (@ronnback ),

Thanks for the reply. I am using the following versions:
Vivado 2020.1
Questa 2019.4_1

According to the release notes (ug973) for Vivado 2020.1, the compatible version is 2019.4. We don’t have that exact version installed, but I assumed the 2019.4_1 would also be compatible.

I will not run the ‘make install-unisim’.

When I run this:
make map_xilinx_7series_lib GRLIB_SIMULATOR=“Questa”

I don’t see any errors, and I don’t see errors in the ‘compile_simlib.log’.

Output when running that command:

GRLIB settings:
GRLIB = /mtcnas/project/janus/mnorris/gaisler_grlib/grlib-gpl-2021.1-b4265
GRLIB_CONFIG is library default
GRLIB_SIMULATOR = Questa
TECHLIBS setting = apa proasic3 axcelerator ec fusion unisim virtex virtex5 secureip unimacro > altera altera_mf stratixii eclipsee cycloneiii stratixiii synplify simprim stratixiv proasic3e proasic3l smartfusion2 rtg4 polarfire nx ihp25 sgb25vrh ut025crh virage rh_lib18t rh_lib18t_io2 rh_lib13t atc18 artisan umc18 virage90 tsmc90 dare nextreme atc18rha_cell smic13 tm65gplus st65lp st65gp cmos9sf nextreme2 gf65g saed32 gf22fdx
Top-level design =
Simulation top-level =
Scanning libraries:
grlib: stdlib util sparc riscv modgen amba dftlib generic_bm
ec: orca
unisim: ise
secureip: ise
unimacro: ise
altera: simprims
altera_mf: simprims
stratixii: simprims
eclipsee: simprims
cycloneiii: simprims
stratixiii: simprims
simprim: vcomponents
virage: vcomponents simprims
atc18: components
umc18: components
saed32: components
techmap: gencomp alltech inferred ec unisim virtex virtex5 altera_mf stratixii eclipsee cycloneiii > stratixiii stratixiv virage atc18 umc18 saed32 maps
spw: comp wrapper
eth: comp core wrapper
opencores: can i2c ge_1000baseX
gaisler: arith memctrl srmmu leon3 leon3v3 leon4 irqmp l2cache/pkg can axi misc ambatest net pci > uart sim jtag greth spacewire spacefibre usb ddr gr1553b i2c spi grdmac grdmac2 subsys noelv plic > noelv/subsys leon5 leon5v0
esa: memoryctrl pci
fmf: utilities flash fifo
spansion: flash
gsi: ssram
micron: sdram
cypress: ssram
work: debug

****** Vivado v2020.1 (64-bit)
**** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
**** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [Common 17-1239] XILINX_LOCAL_USER_DATA is set to ‘0’.
source ./xilinx_lib/_simlib.tcl
compile_simlib -quiet -directory ./xilinx_lib/ -family all -language all -simulator questa → no_ip_compile -library unisim -library simprim
INFO: [Common 17-206] Exiting Vivado at Tue Jun 29 10:49:18 2021…
QuestaSim-64 vmap 2019.4_1 Lib Mapping Utility 2019.11 Nov 12 2019
vmap secureip_ver ./xilinx_lib/secureip
Modifying modelsim.ini
QuestaSim-64 vmap 2019.4_1 Lib Mapping Utility 2019.11 Nov 12 2019
vmap secureip ./xilinx_lib/secureip
Modifying modelsim.ini
QuestaSim-64 vmap 2019.4_1 Lib Mapping Utility 2019.11 Nov 12 2019
vmap axi_bfm ./xilinx_lib/secureip
Modifying modelsim.ini
QuestaSim-64 vmap 2019.4_1 Lib Mapping Utility 2019.11 Nov 12 2019
vmap unisims_ver ./xilinx_lib/unisims_ver
Modifying modelsim.ini
QuestaSim-64 vmap 2019.4_1 Lib Mapping Utility 2019.11 Nov 12 2019
vmap unisim ./xilinx_lib/unisim
Modifying modelsim.ini
QuestaSim-64 vmap 2019.4_1 Lib Mapping Utility 2019.11 Nov 12 2019
vmap unimacro_ver ./xilinx_lib/unimacro_ver
Modifying modelsim.ini
QuestaSim-64 vmap 2019.4_1 Lib Mapping Utility 2019.11 Nov 12 2019
vmap unimacro ./xilinx_lib/unimacro
Modifying modelsim.ini
QuestaSim-64 vmap 2019.4_1 Lib Mapping Utility 2019.11 Nov 12 2019
vmap simprim_ver ./xilinx_lib/simprims_ver
Modifying modelsim.ini
QuestaSim-64 vmap 2019.4_1 Lib Mapping Utility 2019.11 Nov 12 2019
vmap unifast_ver ./xilinx_lib/unifast_ver
Modifying modelsim.ini
QuestaSim-64 vmap 2019.4_1 Lib Mapping Utility 2019.11 Nov 12 2019
vmap unifast ./xilinx_lib/unifast_ver
Modifying modelsim.ini

Then when I do:
cd designs/leon3mp
make sim GRLIB_SIMULATOR=“Questa”

I get:

** Error: (vcom-11) Could not find unisim.vcomponents.
…/…/lib/techmap/unisim/memory_ultrascale.vhd(33): use UNISIM.vcomponents.all;
** Error (suppressible): …/…/lib/techmap/unisim/memory_ultrascale.vhd(33): (vcom-1195)
Cannot find expanded name “unisim.vcomponents”.
** Error: …/…/lib/techmap/unisim/memory_ultrascale.vhd(33): Unknown expanded name.
…/…/lib/techmap/unisim/memory_ultrascale.vhd(38): entity ultrascale_syncram is
** Note: …/…/lib/techmap/unisim/memory_ultrascale.vhd(38): VHDL Compiler exiting

Thanks for any help,
Mike

Hi Mike,

Can you try compiling the simulation libraries without the -quiet flag, which is added by the GRLIB script environment? It could be that something is happening during compilation. Unfortunately I don’t have access to Questa 2019.4_1, so I haven’t been able to check this myself.

Best regards,
Martin

Martin (@ronnback ),

I removed the -quiet flag from the compile. See the output below. I don’t see any errors. Apologies for the long post, it doesn’t appear I can attach anything but images.

Also, see my earlier error when trying to use the JTAG tap controller:

[DRC INBB-3] Black Box Instances: Cell ‘ahbjtaggen0.ahbjtag0/tap0/inf.u0’ of type >‘tap_gen’ has undefined contents and is considered a black box.
The contents of this cell must be defined for opt_design to complete successfully.

Is it possible the ‘tap_gen’ entity/architecture are missing from the GRLIB delivery? We are interested in using the JTAG debug option for the Leon3.

Thanks,
Mike

GRLIB settings:
GRLIB = /mtcnas/project/janus/mnorris/gaisler_grlib/grlib-gpl-2021.1-b4265
GRLIB_CONFIG is library default
GRLIB_SIMULATOR = Questa
TECHLIBS setting = apa proasic3 axcelerator ec fusion unisim virtex virtex5 secureip unimacro altera altera_mf stratixii eclipsee cycloneiii stratixiii synplify simprim stratixiv proasic3e proasic3l smartfusion2 rtg4 polarfire nx ihp25 sgb25vrh ut025crh virage rh_lib18t rh_lib18t_io2 rh_lib13t atc18 artisan umc18 virage90 tsmc90 dare nextreme atc18rha_cell smic13 tm65gplus st65lp st65gp cmos9sf nextreme2 gf65g saed32 gf22fdx
Top-level design =
Simulation top-level =
Scanning libraries:
grlib: stdlib util sparc riscv modgen amba dftlib generic_bm
ec: orca
unisim: ise
secureip: ise
unimacro: ise
altera: simprims
altera_mf: simprims
stratixii: simprims
eclipsee: simprims
cycloneiii: simprims
stratixiii: simprims
simprim: vcomponents
virage: vcomponents simprims
atc18: components
umc18: components
saed32: components
techmap: gencomp alltech inferred ec unisim virtex virtex5 altera_mf stratixii eclipsee cycloneiii stratixiii stratixiv virage atc18 umc18 saed32 maps
spw: comp wrapper
eth: comp core wrapper
opencores: can i2c ge_1000baseX
gaisler: arith memctrl srmmu leon3 leon3v3 leon4 irqmp l2cache/pkg can axi misc ambatest net pci uart sim jtag greth spacewire spacefibre usb ddr gr1553b i2c spi grdmac grdmac2 subsys noelv plic noelv/subsys leon5 leon5v0
esa: memoryctrl pci
fmf: utilities flash fifo
spansion: flash
gsi: ssram
micron: sdram
cypress: ssram
work: debug

****** Vivado v2020.1 (64-bit)
**** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
**** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [Common 17-1239] XILINX_LOCAL_USER_DATA is set to ‘0’.
source ./xilinx_lib/_simlib.tcl

compile_simlib -directory ./xilinx_lib/ -family all -language all -simulator questa -no_ip_compile -library unisim -library simprim

INFO: [Vivado 12-5496] Finding simulator executables and checking version…
WARNING: [Vivado 12-5495] Detected incompatible questasim simulator installation version ‘2019’! The supported simulator version for the current Vivado release is ‘2019.4’.
INFO: [Vivado 12-5498] Processing source library information for the selected device family (default:all) …

Compiling libraries for ‘questasim’ simulator in ‘/mtcnas/project/janus/mnorris/gaisler_grlib/grlib-gpl-2021.1-b4265/xilinx_lib’
→ Compiling ‘verilog.secureip’ library…
> Source Library = ‘/mtcnas/tools/xilinx/2020.1/Vivado/2020.1/data/secureip’
> Compiled Path = ‘/mtcnas/project/janus/mnorris/gaisler_grlib/grlib-gpl-2021.1-b4265/xilinx_lib/secureip’
> Log File = ‘/mtcnas/project/janus/mnorris/gaisler_grlib/grlib-gpl-2021.1-b4265/xilinx_lib/secureip/.cxl.verilog.secureip.secureip.lin64.log’

compile_simlib[verilog.secureip]: 0 error(s), 10 warning(s), 20.00 % complete
→ Compiling ‘vhdl.unisim’ library…
> Source Library = ‘/mtcnas/tools/xilinx/2020.1/Vivado/2020.1/data/vhdl/src/unisims’
> Compiled Path = ‘/mtcnas/project/janus/mnorris/gaisler_grlib/grlib-gpl-2021.1-b4265/xilinx_lib/unisim’
> Log File = ‘/mtcnas/project/janus/mnorris/gaisler_grlib/grlib-gpl-2021.1-b4265/xilinx_lib/unisim/.cxl.vhdl.unisim.unisim.lin64.log’
→ Compiling ‘vhdl.unisim:vhdl.unimacro’ library…
> Source Library = ‘/mtcnas/tools/xilinx/2020.1/Vivado/2020.1/data/vhdl/src/unimacro’
> Compiled Path = ‘/mtcnas/project/janus/mnorris/gaisler_grlib/grlib-gpl-2021.1-b4265/xilinx_lib/unimacro’
> Log File = ‘/mtcnas/project/janus/mnorris/gaisler_grlib/grlib-gpl-2021.1-b4265/xilinx_lib/unimacro/.cxl.vhdl.unimacro.unimacro.lin64.log’
compile_simlib[vhdl.unisim:vhdl.unimacro]: 0 error(s), 0 warning(s)
→ Compiling ‘vhdl.unisim:vhdl.unifast’ library…
> Source Library = ‘/mtcnas/tools/xilinx/2020.1/Vivado/2020.1/data/vhdl/src/unifast’
> Compiled Path = ‘/mtcnas/project/janus/mnorris/gaisler_grlib/grlib-gpl-2021.1-b4265/xilinx_lib/unifast’
> Log File = ‘/mtcnas/project/janus/mnorris/gaisler_grlib/grlib-gpl-2021.1-b4265/xilinx_lib/unifast/.cxl.vhdl.unifast.unifast.lin64.log’
compile_simlib[vhdl.unisim:vhdl.unifast]: 0 error(s), 0 warning(s)

compile_simlib[vhdl.unisim]: 0 error(s), 0 warning(s), 60.00 % complete
→ Compiling ‘verilog.unisim’ library…
> Source Library = ‘/mtcnas/tools/xilinx/2020.1/Vivado/2020.1/data/verilog/src’
> Compiled Path = ‘/mtcnas/project/janus/mnorris/gaisler_grlib/grlib-gpl-2021.1-b4265/xilinx_lib/unisims_ver’
> Log File = ‘/mtcnas/project/janus/mnorris/gaisler_grlib/grlib-gpl-2021.1-b4265/xilinx_lib/unisims_ver/.cxl.verilog.unisim.unisims_ver.lin64.log’
→ Compiling ‘verilog.unisim:verilog.unimacro’ library…
> Source Library = ‘/mtcnas/tools/xilinx/2020.1/Vivado/2020.1/data/verilog/src/unimacro’
> Compiled Path = ‘/mtcnas/project/janus/mnorris/gaisler_grlib/grlib-gpl-2021.1-b4265/xilinx_lib/unimacro_ver’
> Log File = ‘/mtcnas/project/janus/mnorris/gaisler_grlib/grlib-gpl-2021.1-b4265/xilinx_lib/unimacro_ver/.cxl.verilog.unimacro.unimacro_ver.lin64.log’
compile_simlib[verilog.unisim:verilog.unimacro]: 0 error(s), 0 warning(s)
→ Compiling ‘verilog.unisim:verilog.unifast’ library…
> Source Library = ‘/mtcnas/tools/xilinx/2020.1/Vivado/2020.1/data/verilog/src/unifast’
> Compiled Path = ‘/mtcnas/project/janus/mnorris/gaisler_grlib/grlib-gpl-2021.1-b4265/xilinx_lib/unifast_ver’
> Log File = ‘/mtcnas/project/janus/mnorris/gaisler_grlib/grlib-gpl-2021.1-b4265/xilinx_lib/unifast_ver/.cxl.verilog.unifast.unifast_ver.lin64.log’
compile_simlib[verilog.unisim:verilog.unifast]: 0 error(s), 0 warning(s)

compile_simlib[verilog.unisim]: 0 error(s), 0 warning(s), 80.00 % complete
→ Compiling ‘verilog.simprim’ library…
> Source Library = ‘/mtcnas/tools/xilinx/2020.1/Vivado/2020.1/data/verilog/src/unisims’
> Compiled Path = ‘/mtcnas/project/janus/mnorris/gaisler_grlib/grlib-gpl-2021.1-b4265/xilinx_lib/simprims_ver’
> Log File = ‘/mtcnas/project/janus/mnorris/gaisler_grlib/grlib-gpl-2021.1-b4265/xilinx_lib/simprims_ver/.cxl.verilog.simprim.simprims_ver.lin64.log’

compile_simlib[verilog.simprim]: 0 error(s), 0 warning(s), 100.00 % complete
Copying setup file ‘modelsim.ini’ to ‘/mtcnas/project/janus/mnorris/gaisler_grlib/grlib-gpl-2021.1-b4265/./xilinx_lib//modelsim.ini’ …


  •                                         COMPILATION SUMMARY                                                     *
    
  •                                                                                                                 *
    
  • Simulator used: questasim *
  • Compiled on: Tue Jul 6 09:54:17 2021 *
  •                                                                                                                 *
    

  • Library | Language | Mapped Library Name | Error(s) | Warning(s) *
    ---------------------------------------------------------------------------------------------------------------------
  • secureip | verilog | secureip | 0 | 10 *

  • unisim | vhdl | unisim | 0 | 0 *

  • unimacro | vhdl | unimacro | 0 | 0 *

  • unifast | vhdl | unifast | 0 | 0 *

  • unisim | verilog | unisims_ver | 0 | 0 *

  • unimacro | verilog | unimacro_ver | 0 | 0 *

  • unifast | verilog | unifast_ver | 0 | 0 *

  • simprim | verilog | simprims_ver | 0 | 0 *

INFO: [Vivado 12-7167] Writing compiled library information…
INFO: [Vivado 12-7165] Finished writing compiled library information.
compile_simlib: Time (s): cpu = 00:31:59 ; elapsed = 00:33:47 . Memory (MB): peak = 2209.219 ; gain = 0.004 ; free physical = 6044 ; free virtual = 85804
INFO: [Common 17-206] Exiting Vivado at Tue Jul 6 10:28:03 2021…
QuestaSim-64 vmap 2019.4_1 Lib Mapping Utility 2019.11 Nov 12 2019
vmap secureip_ver ./xilinx_lib/secureip
Modifying modelsim.ini
QuestaSim-64 vmap 2019.4_1 Lib Mapping Utility 2019.11 Nov 12 2019
vmap secureip ./xilinx_lib/secureip
Modifying modelsim.ini
QuestaSim-64 vmap 2019.4_1 Lib Mapping Utility 2019.11 Nov 12 2019
vmap axi_bfm ./xilinx_lib/secureip
Modifying modelsim.ini
QuestaSim-64 vmap 2019.4_1 Lib Mapping Utility 2019.11 Nov 12 2019
vmap unisims_ver ./xilinx_lib/unisims_ver
Modifying modelsim.ini
QuestaSim-64 vmap 2019.4_1 Lib Mapping Utility 2019.11 Nov 12 2019
vmap unisim ./xilinx_lib/unisim
Modifying modelsim.ini
QuestaSim-64 vmap 2019.4_1 Lib Mapping Utility 2019.11 Nov 12 2019
vmap unimacro_ver ./xilinx_lib/unimacro_ver
Modifying modelsim.ini
QuestaSim-64 vmap 2019.4_1 Lib Mapping Utility 2019.11 Nov 12 2019
vmap unimacro ./xilinx_lib/unimacro
Modifying modelsim.ini
QuestaSim-64 vmap 2019.4_1 Lib Mapping Utility 2019.11 Nov 12 2019
vmap simprim_ver ./xilinx_lib/simprims_ver
Modifying modelsim.ini
QuestaSim-64 vmap 2019.4_1 Lib Mapping Utility 2019.11 Nov 12 2019
vmap unifast_ver ./xilinx_lib/unifast_ver
Modifying modelsim.ini
QuestaSim-64 vmap 2019.4_1 Lib Mapping Utility 2019.11 Nov 12 2019
vmap unifast ./xilinx_lib/unifast_ver
Modifying modelsim.ini

-Mike

Hi Mike,

The inferred TAP is not included in the GPL package.

It is strange the simulator can not find unisim.vcomponents, since it seems to be compiled. I haven’t been able to reproduce this.

Under xilinx_lib/unisim/ there should be a file called .cxl.vhdl.unisim.unisim.lin64.cmf, listing which files under unisim that are compiled.

Best regards,

Martin

Martin (@ronnback ),

I see that .cxl file. The only line that has anything including “vcomp” is:

/mtcnas/tools/xilinx/2020.1/Vivado/2020.1/data/vhdl/src/unisims/unisim_retarget_VCOMP.vhdp

So you are saying that if we are intending to target the “inferred” technology, then we cannot use the JTAG debug option? Has that always been the case? I am discussing my experience with another group, and they had used an older GRLIB (2017.2), and I believe they also targeted “inferred” technology, and had enabled the JTAG debug option.

Thanks,
Mike

Hi Mike,

tap_inferred.vhd has not been in the GPL package previously, only in commercial packages.

Best regards,
Martin

Martin,

Okay thanks for the clarification. Any insight into the problem with my compilation?
I still get this:

** Error: (vcom-11) Could not find unisim.vcomponents.
…/…/lib/techmap/unisim/memory_ultrascale.vhd(33): use >UNISIM.vcomponents.all;
** Error (suppressible): …/…/lib/techmap/unisim/memory_ultrascale.vhd(33): (vcom->1195) Cannot find expanded name “unisim.vcomponents”.
** Error: …/…/lib/techmap/unisim/memory_ultrascale.vhd(33): Unknown expanded name.
…/…/lib/techmap/unisim/memory_ultrascale.vhd(38): entity ultrascale_syncram is
** Note: …/…/lib/techmap/unisim/memory_ultrascale.vhd(38): VHDL Compiler exiting

Thanks,
Mike

No, unfortunately not. I haven’t been able to reproduce it with the versions of the tools I have access to. This error suggests that vcomponents haven’t been properly compiled or mapped.

Best regards,
Martin

Martin (@ronnback ),

Thanks for your help looking into this. I’m a bit confused about the JTAG debug option. As I mentioned, we are targeting the Zynq Ultrascale+ MPSoC. Since there are no design examples for this board, I had to select “inferred” for the technology. Are you saying there is no TAP controller included for the “inferred” option? How do users use the JTAG debug option, when they are targeting designs that are not included in the examples?

Thanks,
Mike