Design Compiler and Formality tool of synopsys showing error in RTL code

NOEL-V
1

For Microcontroller Version with 32 bits

Following lines showing error in code during synthesis or/and formality.

  1. File Name : nvsupport.vhd - LINE NO. 8438 to 8445 ( Reason : wdata size 32 bit and function try to access bits higher then 31 )
  2. File Name : cctrlnv.vhd - LINE NO. 469 to 470 ( Reason : mask’length = 2 , Requirement : mask’length = 3, )
  3. File Name : iunv.vhd -LINE NO. 10577 to 10578 ( Reason : XLEN = 32 , Requirement : XLEN > 32, Note : Working Fine for GP 64 bit Version )
  4. File Name : mmuconfig.vhd - Line No. 644 ( Reason : vmid_len= 0, Requirement : vmid_len> 0, Note : Working Fine for GP 32/64 bit Version )
2

Hi Chiragkumar,

Could you clarify which GRLIB version you are using? There were some fixes in the NOEL-V for Design Compiler and Formality in the latest release 2025.1, so just wondering if you are using an older one and the problem is already fixed.

Thanks,
Joaquin

3

I am using Latest release of GRLIB - download on 10 April 2025.

All Error in Std_logic_vector invalid access ..

for instance

signal y : std_logic_vector ( 22 + x -1 downto 22);
value of x =0 passed by function/genric

Hence signal y : std_logic_vector (21 downto 22);

It become invalid and tool through error…