Logic Equivalence Check using formality tool having fatal error for cctrlnv.vhd and cpucorenv.vhd

[Chiragkumar]

For Release 2024.4-b4295

I am performing equivalency check of RTL and netlist (generated using Design Compiler) using formality tool of Synopsys. cctrlnv.vhd and cpucorenv.vhd file shows fatal error during execution of set_top command. This error is shown for all configuration (GP, HP, Lite, Microcontroller, 32/64 bit etc.). Fatal error images are attached herewith for your reference.

My proposed configuration 32-bit RISC processor with GP. Kindly provide the updated file for my evaluation.

[joaquin.espana]

Hi Chiragkumar,

The release 2025.1-b4296 has been published now, which includes some fixes for the NOEL-V core. Could you rerun the flow and confirm that this has been solved?

Thanks,
Joaquin