The 'reg' command can not show the FPU registers

General - Software
1

The ‘float’ and ‘reg’ command can not show the FPU registers:

  GRMON debug monitor v3.3.10 64-bit eval version

grmon3> float
  FPU Disabled!

grmon3> reg
  a0: 0000000000000001    t0: ffffffff82a035c0    s0: ffffffff83003f60
  a1: 0000000000000000    t1: 0000000000000000    s1: 0000000000000000
  a2: ffffffd8bc4e6000    t2: 000000000000001f    s2: ffffffff831011e8
  a3: ffffffff831016f0    t3: 000000000000018c    s3: 0000000000000007
  a4: 0000000000000000    t4: 00000000000003ff    s4: ffffffff83101390
  a5: 0000000000000000    t5: 0000001a00000000    s5: 0000000000000000
  a6: 4000000000000000    t6: 0000000091c3d373    s6: ffffffff828be400
  a7: 0000000054494d45                            s7: ffffffff83137c70
                                                  s8: 0000000000000000
  Supervisor mode         sp: ffffffff83003ea0    s9: 0000000000000000
  FPU disabled            tp: ffffffff8300dac0   s10: 0000000000000000
  IRQ disabled            gp: ffffffff830ffd30   s11: 0000000000000000

  ra: ffffffff800489e6
  pc: ffffffff8009006c   sd      s7, 8(sp)

grmon3> info sys dm0
  dm0        Frontgrade Gaisler  RISC-V Debug Module
             AHB Master 9
             AHB: f6000000 - f7000000
             hart0: DXLEN 64, MXLEN 64, SXLEN 64, UXLEN 64
                    ISA A C D F H I M X,  Modes M S U
                    Stack pointer 0xbffffff0
                    icache 4 * 4 kB, 32 B/line, dir
                    dcache 4 * 4 kB, 32 B/line, dir
                    5 triggers,
                    itrace 64 lines
             hart1: DXLEN 64, MXLEN 64, SXLEN 64, UXLEN 64
                    ISA A C D F H I M X,  Modes M S U
                    Stack pointer 0xbffffff0
                    icache 4 * 4 kB, 32 B/line, dir
                    dcache 4 * 4 kB, 32 B/line, dir
                    5 triggers,
                    itrace 64 lines
             hart2: DXLEN 64, MXLEN 64, SXLEN 64, UXLEN 64
                    ISA A C D F H I M X,  Modes M S U
                    Stack pointer 0xbffffff0
                    icache 4 * 4 kB, 32 B/line, dir
                    dcache 4 * 4 kB, 32 B/line, dir
                    5 triggers,
                    itrace 64 lines
             hart3: DXLEN 64, MXLEN 64, SXLEN 64, UXLEN 64
                    ISA A C D F H I M X,  Modes M S U
                    Stack pointer 0xbffffff0
                    icache 4 * 4 kB, 32 B/line, dir
                    dcache 4 * 4 kB, 32 B/line, dir
                    5 triggers,
                    itrace 64 lines

grmon3>

but Linux can run normally on hardware FPU:

# uname -a
Linux buildroot 6.3.0 #1 SMP Wed Apr 24 11:27:11 CST 2024 riscv64 GNU/Linux

# cat /proc/cpuinfo
processor       : 0
hart            : 0
isa             : rv64imafdc
mmu             : sv39
mvendorid       : 0x324
marchid         : 0x0
mimpid          : 0x0

processor       : 1
hart            : 1
isa             : rv64imafdc
mmu             : sv39
mvendorid       : 0x324
marchid         : 0x0
mimpid          : 0x0

processor       : 2
hart            : 2
isa             : rv64imafdc
mmu             : sv39
mvendorid       : 0x324
marchid         : 0x0
mimpid          : 0x0

processor       : 3
hart            : 3
isa             : rv64imafdc
mmu             : sv39
mvendorid       : 0x324
marchid         : 0x0
mimpid          : 0x0
2

GRMON will not print the registers if the FPU is disabled in mstatus. If you set it in mstatus (bit 14:13) it should work.

I will check if GRMON should enable it in mstatus during startup.