Nexys-Video Leon3 GRLIB Conversion to Opal Kelly XEM7310

LEON
1

I am working on a project that involves porting the GRLIB Leon3 Design for the Digilent Nexys-Video board onto the Opal Kelly XEM7310 Board.

I have built the project in Vivado, changed the FPGA in the project settings and updated the constraints file with a known pinout for the XEM7310.

I have also updated the mig settings according to Opal Kelly’s XEM7310 settings here: DDR3 Memory - Opal Kelly Documentation Portal
However, this involved changing the existing single-ended clock to a differential, which meant I had to change ‘sys_clk_i’ to ‘sys_clk_p’ & ‘sys_clk_n’ in the top level and mig instances.

This design successfully synthesizes, now though, I am encountering these errors when running implementation:

  • [Netlist 29-160] Cannot set property ‘IOSTANDARD’, because the property does not exist for objects of type ‘pin’.
    [“/opt/grlib-gpl-2023.2-b4283/designs/leon3-digilent-nexys-video/vivado/leon3-digilent-nexys-video/leon3-digilent-nexys-video.gen/sources_1/ip/mig/mig/user_design/constraints/mig.xdc”:379]

  • [DRC REQP-61] ibufds_connects_I_active: IBUFDS mig_gen.gen_mig.ddrc/MCB_inst/u_mig_mig/u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk pin I has an invalid driver

  • [DRC REQP-62] ibufds_connects_IB_active: IBUFDS mig_gen.gen_mig.ddrc/MCB_inst/u_mig_mig/u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk pin IB has an invalid driver

Which I believe has to do with the new sys_clks not getting buffered correctly in the top level.

Am I missing something in Leon design or is there another fix to these errors?

2

Hi Hamilton,

Are you instantiating any buffer in the top level, between the pins and the Xilinx memory controller?

One thing you could do is to leave the memory controller unaltered when it comes to the input clock; that is, leaving it to single edge. And then, in the leon3mp.vhd top level, instantiate a differential buffer IBUFDS, with inputs ‘sys_clk_p’ and ‘sys_clk_n’ and output ‘sysclk’ (or ‘sys_clk_i’, if you changed the name of that signal). Maybe worth a short rebuilding to see if it makes a difference?

In the design leon3-digilent-nexys-video design I see that the input clock sysclk goes to a clock generator (clkgenmigin) as well. Are you keeping that one? In that case, you may need to instantiate the differential pads in the RTL and not in the MIG.

I believe that the Xilinx memory controller will internally instantiate differential buffers (IBUFDS) if you set the input clock type to differential, in which case you cannot drive any other IP with that input clock, I believe. Basically, you would need to make sure that the differential clock is connected to the MIG directly and nothing else, and then the clock generated by the memory controller could drive the rest of the logic. Just a thought, in case the above solution doesn’t work - I can provide a bit more guidance if needed to make this conversion.

Regards,
Joaquin