I am working on a project that involves porting the GRLIB Leon3 Design for the Digilent Nexys-Video board onto the Opal Kelly XEM7310 Board.
I have built the project in Vivado, changed the FPGA in the project settings and updated the constraints file with a known pinout for the XEM7310.
I have also updated the mig settings according to Opal Kelly’s XEM7310 settings here: DDR3 Memory - Opal Kelly Documentation Portal
However, this involved changing the existing single-ended clock to a differential, which meant I had to change ‘sys_clk_i’ to ‘sys_clk_p’ & ‘sys_clk_n’ in the top level and mig instances.
This design successfully synthesizes, now though, I am encountering these errors when running implementation:
[Netlist 29-160] Cannot set property ‘IOSTANDARD’, because the property does not exist for objects of type ‘pin’.
[DRC REQP-61] ibufds_connects_I_active: IBUFDS mig_gen.gen_mig.ddrc/MCB_inst/u_mig_mig/u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk pin I has an invalid driver
[DRC REQP-62] ibufds_connects_IB_active: IBUFDS mig_gen.gen_mig.ddrc/MCB_inst/u_mig_mig/u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk pin IB has an invalid driver
Which I believe has to do with the new sys_clks not getting buffered correctly in the top level.
Am I missing something in Leon design or is there another fix to these errors?