Leon processor on FPGA zinq xc7z020

General - GRLIB SoC
1

Hello colleagues.
I am trying to implement Leon processor on FPGA zinq xc7z020.
The design “leon3-zedboard-xc7z020” was used as a basis.
Development is carried out on Vivado 2018.2, while the difficulties of importing scripts from version 2013.4 were overcome.

  1. The way of our development:
  • the composition of the project in “make xconfig” has not changed!
  • Constraints have been replaced with Leds, Switchs, Buttons
  • changed clock settings FCLK_CLK0 in PS7 and Constraints at 50 MHz (according to the documentation for my board)
  • there is only one user LED on our board and it is connected to the “AHB HREADY signal”
  • Design, implementation went without errors with the implementation of time constraints
  • “leon3mp.bit” was formed
  • loading is made by the following commands in the “XSCT”:
    ==========================================================================
    xsct% connect
    attempting to launch hw_server
    ****** Xilinx hw_server v2018.2
    **** Build date : Jun 14 2018-20:42:52
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
    INFO: hw_server application started
    INFO: Use Ctrl-C to exit hw_server application
    ****** Xilinx hw_server v2018.2
    **** Build date : Jun 14 2018-20:42:52
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
    INFO: hw_server application started
    INFO: Use Ctrl-C to exit hw_server application
    INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121
    tcfchan#1
    xsct% targets
    xsct% Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0x0 (Suspended)
    xsct% Info: ARM Cortex-A9 MPCore #1 (target 3) Stopped at 0xffffff34 (Suspended)
    xsct% targets 2
    xsct% rst
    Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0xffffff28 (Suspended)
    Info: ARM Cortex-A9 MPCore #1 (target 3) Stopped at 0xffffff34 (Suspended)
    xsct% fpga -f leon3mp.bit
    100% 3MB 1.7MB/s 00:02
    xsct% source ps7_init.tcl
    xsct% ps7_init
    xsct% ps7_post_config
    xsct% disconnect
    ==========================================================================
  1. As a result:
  • LED “AHB HREADY signal” is on
  • when connected by the “GRMON” program, we have the message:
    ==========================================================================
    JTAG chain (2): xc7x020 zynq7000_arm_dap
    AMBA plug&play not found!
    Failed to initialize target!
    ==========================================================================

Help is needed.
How to understand that the processor is working?
Can I add a Debug core to my project?
What signals to connect to Debug?
What does an “AHB HREADY signal” actually mean?

Thanks in advance,
Voland vasiapupkins1812@gmail.com

2

Addition:

  • when the signal “error mode, execution halted” is connected to the LED, the LED is on
  • System reset is mapped on the button and does not change the state of the system
3

Hello Voland,

This design was contributed to GRLIB by a user, and I have not built or used it myself so I can just give some general pointers.

From what I understand from the README the processor system needs to be setup properly so the LEON system gets a clock. If you have been changing the scripts to work with newer Vivado maybe that’s broken. One simple way to debug if the clock is there could be to add a counter in FPGA design and take a high bit of the counter out to a LED to see that the clock in the LEON system is actually clocked.

Regards,
Magnus

4

Hello, Magnus

Thanks for the tip

  1. We connected the LED to the “clkm” signal via a frequency divider counter. When setting the division factor of 50 million, we see a blinking of 1 hertz, which corresponds to the given clock frequency.
  2. We tried to make a branch of the clock frequency signal for memory, as from our point of view, the most important frequency. This operation ended in failure. There is no way we can overcome errors related to signal buffering.
    When connecting the counter to the “processing_system7_0_DDR_Clk” signal, we get errors:
  • [DRC RPBF-3] IO port buffering is incomplete: Device port processing_system7_0_DDR_Clk_BUF expects both input and output buffering but the buffers are incomplete.
  • [Place 30-69] Instance processing_system7_0_DDR_Clk_BUF_OBUF_inst (OBUF drives I / O terminal processing_system7_0_DDR_Clk_BUF) is unplaced after IO placer

Can you tell us what signals to look for next after we have found the normal clock speed of the entire LEON circuit?

Regards,
Voland