GRLIB GPL 2023.1 released

The development team is pleased to announce the release of GRLIB GPL 2023.1-b4282, which is now available for download from:

Bitfile and netlist packages are available via:

The changelog is here:

and is also reproduced below.

Some of the highlights are:

  • NOEL-V and RISC-V peripherals updates: interrupt controller, watchdog, UART interface register, debug module, new ISA extensions, etc. Bug fixes and other improvements.
  • LEON5: Improved store performance. Cache controller updates. Bug fixes and other improvements.
  • APBUART: Fixed bug where two stopbits were only sent when parity was enabled. Modification of simulation mode (console=1).
  • General IP updates

Updated example bitstreams for LEON5 and NOEL-V are available for download from:

If you find any any reproducible bugs or issues please don’t hesitate to post in the community.

----------------------- Release 2023.1-b4282 ---------------------------

2023-04-27 LEON5: Minor fix to snooping on stores. Stores and atomics to ASI 1 activated the snooping and caused the cache line to be invalidated unnecessarily.

2023-04-27 LEON5: Bug fix for diagnostic data cache tag access (ASI 0x0E). Valid bits could be read out incorrectly in configurations where the valid bits are held in flip flops (cmemconf=2).

2023-04-27 LEON5: Bug fixes for MMU TLB flush and probe (ASI 0x1B).

2023-04-18 LEON5: Bugfix for AHB retry corner case during DCache fetch

2023-04-11 LEON5: Bugfix for breaking execution from debug module while an atomic operation is in progress.

2023-04-06 NOEL-V: NOEL-V and RISC-V peripherals updates

  • Added AIA interrupt controller (disabled in default config.)
  • Added ACLINT to replacing CLINT
  • Added UART interface register compatible with 16550 spec.
  • Added RISC-V watchdog
  • Debug module updates (removed internal AHB2AHB bridge)
  • PnP for NOELVSYS is updated to place internal APB bus first.
  • TLB flush updates (separate flush for sTLB and hTLB, Address/VMID/ASID matching)
  • Added Diagnostic access to TLBs
  • Update STVEC/VSTVEC to have 256 byte alignment in vectored mode.
  • Added ISA extensions:
    • Zcb, Zfhmin, Zfh, Smstateen
    • Smepmp, Zicond, Zfa, Smrnmi (experimental)
  • Bug fixes:
    • Store byte followed by sfence.vma prevent update the cache
    • Instruction c.zext.w was not illegal on 32-bit version
    • Zicbom instructions could operate in incorrect cache line
    • Incorrect mask for hedeleg
    • Minor FPU updates

2023-03-30 LEON5: Minor fixes for debug module access while cache controller still has an ongoing access.

2023-03-27 SYNCFIFO_2P: Add scantest generic to propagate down to syncram_2p instances.

2023-03-06 LEON5: Increase number of timers in the gptimer in standard LEON5SYS configurations from 2 to 3.

2023-02-09 APBUART systest: Fix to the initial loop to fill the holding register to avoid X issues in simulation.

2023-02-07 LEON5: Bug fixes related to breaking/resuming execution and single stepping.

2023-01-30 APBUART: Modification of simulation mode (console=1). When console=1, reads of the status register now return values consistent with the transmitter shift register and transmitter FIFO being empty. This should make the console=1 configuration compatible with existing software. Notably, BCC2 was not entirely compatible prior to this change.

2023-01-23 LEON5: Cache controller updates:

  • Added write combining feature for double stores, enabled via LEON5 configuration register bit. Combines stores to consecutive addresses into larger bursts up to cache line boundary.
  • Minor change to debug access handling in order to remove some timing critical paths.
  • Fixes to HPROT generation for store accesses, bit 1 not always reflecting supervisor status correctly for that store.

2023-01-11 LEON5: Various improvements / fixes related to stores

  • Make stores propagate through to the AHB bus one cycle faster in some cases.
  • Make HBURST drive HBURST_SINGLE for MMU page table accesses (to allow for re-arbitration in the AHB arbiter).
  • Ensure bus lock is always dropped between locked store and any following regular stores.
  • Bug fixes to HBUSREQ signal generation and RETRY/SPLIT handling during 32-bit write burst (double store to narrow area functionality added recently).

2022-12-21 APBUART:

  • Fixed bug where two stopbits were only sent when parity was enabled.
  • GRIP: stopbit setting has no effect on the receiver
  • GRIP: corrected description of receiver input filtering
  • GRIP: parity gen

2022-12-20 LEON5: Improved store performance when used with 32-bit AHB buses. Stores to narrow (32-bit) areas now go through the store buffer/FIFO without blocking the pipeline similar to the wider case, with double stores performed as two-beat bursts.

1 Like

Hello Joaquin,

I want to report an issue with the newly released noelv-digilent-arty-a7 design ( from grlib-gpl-2023.1-b4282). I’m using the Vivado Simulator to simulate the design and found the waveform failed to load. The bug lies in the $GRLIB/lib/gaisler/noelv/core/utilnv.vhd:276.

I don’t think the Vivado Simulator is incompatible with the design because the same design from grlib-gpl-2022.4-b4280 can be simulated with no error.

I’m looking forward to your feedback.

Best regard,



this turned out to be a rather tricky issue to deal with, but I have now been able to get a simulation of the GPL noelv-digilent-arty-a7 to run under XSIM for Vivado 2018.1.

Different versions of Vivado XSIM apparently crash for different reasons, but with a series of minor rewrites both 2018.1 and 2022.2 have now started up properly. Unfortunately, 2022.2 has deeper issues and will not actually simulate the default ram.srec correctly.

We will make sure to get improved XSIM support into our next release. Given the error you reported, your version seems to behave better than the ones I have tested (I got multiple crashes without information during elaboration), so the following might be enough to clear up the issue for you:

In iunv.vhd / dcache_gen():

variable x0_rs1 : std_ulogic;
variable x0_rs2 : std_ulogic;

x0_rs1 := all_0(rs1(inst_in));
x0_rs2 := all_0(rs2(inst_in));

The only change was a move of the initialization of the two variables. Obviously, this is not supposed to make a difference, but I got exactly the same crash in utilnv.vhd without it.

Johan Klockars