Why can’t I compile testlib.vhd for grlib. Modelsim is giving me errors about function and procedure overloading. Shouldn’t this compile right off the bat?
– Compiling package body testlib
– Loading package testlib
** Error: C:/Users/ssheikh/Desktop/LEMS/grlib-gpl-2020.1-b4251/lib/grlib/stdlib/testlib.vhd(250): Subprogram body for “compare” has already been defined at line 234.
** Error: C:/Users/ssheikh/Desktop/LEMS/grlib-gpl-2020.1-b4251/lib/grlib/stdlib/testlib.vhd(396): (vcom-1602) Subprogram “compare” is ambiguous.
Feasible subprograms are:
(explicit) testlib.compare[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN] at C:/Users/ssheikh/Desktop/LEMS/grlib-gpl-2020.1-b4251/lib/grlib/stdlib/testlib.vhd(234)
(explicit) testlib.compare[STD_ULOGIC_VECTOR, STD_ULOGIC_VECTOR return BOOLEAN] at C:/Users/ssheikh/Desktop/LEMS/grlib-gpl-2020.1-b4251/lib/grlib/stdlib/testlib.vhd(250)
** Error: C:/Users/ssheikh/Desktop/LEMS/grlib-gpl-2020.1-b4251/lib/grlib/stdlib/testlib.vhd(431): Subprogram “WRITE” is ambiguous.
Feasible subprograms are:
(explicit) std_logic_1164.WRITE[std.TEXTIO.LINE, STD_ULOGIC, std.TEXTIO.SIDE, NATURAL] at $MODEL_TECH/…/vhdl_src/ieee/stdlogic.vhd(277)
(explicit) StdIO.Write[std.TEXTIO.LINE, STD_ULOGIC, std.TEXTIO.SIDE, NATURAL] at C:/Users/ssheikh/Desktop/LEMS/grlib-gpl-2020.1-b4251/lib/grlib/stdlib/stdio.vhd(73)
** Error: C:/Users/ssheikh/Desktop/LEMS/grlib-gpl-2020.1-b4251/lib/grlib/stdlib/testlib.vhd(431): (vcom-1600) No feasible entries for subprogram “Write”.
Visible subprograms are:
(explicit) StdIO.Write[std.TEXTIO.LINE, STD_ULOGIC, std.TEXTIO.SIDE, NATURAL] at C:/Users/ssheikh/Desktop/LEMS/grlib-gpl-2020.1-b4251/lib/grlib/stdlib/stdio.vhd(73)
(explicit) NUMERIC_STD.WRITE[std.TEXTIO.LINE, UNRESOLVED_UNSIGNED, std.TEXTIO.SIDE, NATURAL] at vhdl_src/ieee/mti_numeric_std.vhd(2082)
(explicit) NUMERIC_STD.WRITE[std.TEXTIO.LINE, UNRESOLVED_SIGNED, std.TEXTIO.SIDE, NATURAL] at vhdl_src/ieee/mti_numeric_std.vhd(2085)
(explicit) std_logic_1164.WRITE[std.TEXTIO.LINE, STD_ULOGIC, std.TEXTIO.SIDE, NATURAL] at $MODEL_TECH/…/vhdl_src/ieee/stdlogic.vhd(277)
(explicit) std_logic_1164.WRITE[std.TEXTIO.LINE, STD_ULOGIC_VECTOR, std.TEXTIO.SIDE, NATURAL] at $MODEL_TECH/…/vhdl_src/ieee/stdlogic.vhd(280)
(implicit) TEXTIO.write[std.TEXTIO.TEXT, std.STANDARD.STRING] at vhdl_src/std/textio.vhd(15)
(explicit) TEXTIO.WRITE[std.TEXTIO.LINE, BIT, std.TEXTIO.SIDE, NATURAL] at vhdl_src/std/textio.vhd(123)
(explicit) TEXTIO.WRITE[std.TEXTIO.LINE, BIT_VECTOR, std.TEXTIO.SIDE, NATURAL] at vhdl_src/std/textio.vhd(126)
(explicit) TEXTIO.WRITE[std.TEXTIO.LINE, BOOLEAN, std.TEXTIO.SIDE, NATURAL] at vhdl_src/std/textio.vhd(129)
(explicit) TEXTIO.WRITE[std.TEXTIO.LINE, std.STANDARD.CHARACTER, std.TEXTIO.SIDE, NATURAL] at vhdl_src/std/textio.vhd(132)
(explicit) TEXTIO.WRITE[std.TEXTIO.LINE, INTEGER, std.TEXTIO.SIDE, NATURAL] at vhdl_src/std/textio.vhd(135)
(explicit) TEXTIO.WRITE[std.TEXTIO.LINE, std.STANDARD.REAL, std.TEXTIO.SIDE, NATURAL, NATURAL] at vhdl_src/std/textio.vhd(138)
(explicit) TEXTIO.WRITE[std.TEXTIO.LINE, std.STANDARD.REAL, std.STANDARD.STRING] at vhdl_src/std/textio.vhd(142)
(explicit) TEXTIO.WRITE[std.TEXTIO.LINE, std.STANDARD.STRING, std.TEXTIO.SIDE, NATURAL] at vhdl_src/std/textio.vhd(145)
(explicit) TEXTIO.WRITE[std.TEXTIO.LINE, std.STANDARD.TIME, std.TEXTIO.SIDE, NATURAL, std.STANDARD.TIME] at vhdl_src/std/textio.vhd(148)
** Error: C:/Users/ssheikh/Desktop/LEMS/grlib-gpl-2020.1-b4251/lib/grlib/stdlib/testlib.vhd(433): Subprogram “WRITE” is ambiguous.
Feasible subprograms are:
(explicit) std_logic_1164.WRITE[std.TEXTIO.LINE, STD_ULOGIC, std.TEXTIO.SIDE, NATURAL] at $MODEL_TECH/…/vhdl_src/ieee/stdlogic.vhd(277)
(explicit) StdIO.Write[std.TEXTIO.LINE, STD_ULOGIC, std.TEXTIO.SIDE, NATURAL] at C:/Users/ssheikh/Desktop/LEMS/grlib-gpl-2020.1-b4251/lib/grlib/stdlib/stdio.vhd(73)
** Error: C:/Users/ssheikh/Desktop/LEMS/grlib-gpl-2020.1-b4251/lib/grlib/stdlib/testlib.vhd(433): (vcom-1600) No feasible entries for subprogram “Write”.
Visible subprograms are:
(explicit) StdIO.Write[std.TEXTIO.LINE, STD_ULOGIC, std.TEXTIO.SIDE, NATURAL] at C:/Users/ssheikh/Desktop/LEMS/grlib-gpl-2020.1-b4251/lib/grlib/stdlib/stdio.vhd(73)
(explicit) NUMERIC_STD.WRITE[std.TEXTIO.LINE, UNRESOLVED_UNSIGNED, std.TEXTIO.SIDE, NATURAL] at vhdl_src/ieee/mti_numeric_std.vhd(2082)
(explicit) NUMERIC_STD.WRITE[std.TEXTIO.LINE, UNRESOLVED_SIGNED, std.TEXTIO.SIDE, NATURAL] at vhdl_src/ieee/mti_numeric_std.vhd(2085)
(explicit) std_logic_1164.WRITE[std.TEXTIO.LINE, STD_ULOGIC, std.TEXTIO.SIDE, NATURAL] at $MODEL_TECH/…/vhdl_src/ieee/stdlogic.vhd(277)
(explicit) std_logic_1164.WRITE[std.TEXTIO.LINE, STD_ULOGIC_VECTOR, std.TEXTIO.SIDE, NATURAL] at $MODEL_TECH/…/vhdl_src/ieee/stdlogic.vhd(280)
(implicit) TEXTIO.write[std.TEXTIO.TEXT, std.STANDARD.STRING] at vhdl_src/std/textio.vhd(15)
(explicit) TEXTIO.WRITE[std.TEXTIO.LINE, BIT, std.TEXTIO.SIDE, NATURAL] at vhdl_src/std/textio.vhd(123)
(explicit) TEXTIO.WRITE[std.TEXTIO.LINE, BIT_VECTOR, std.TEXTIO.SIDE, NATURAL] at vhdl_src/std/textio.vhd(126)
(explicit) TEXTIO.WRITE[std.TEXTIO.LINE, BOOLEAN, std.TEXTIO.SIDE, NATURAL] at vhdl_src/std/textio.vhd(129)
(explicit) TEXTIO.WRITE[std.TEXTIO.LINE, std.STANDARD.CHARACTER, std.TEXTIO.SIDE, NATURAL] at vhdl_src/std/textio.vhd(132)
(explicit) TEXTIO.WRITE[std.TEXTIO.LINE, INTEGER, std.TEXTIO.SIDE, NATURAL] at vhdl_src/std/textio.vhd(135)
(explicit) TEXTIO.WRITE[std.TEXTIO.LINE, std.STANDARD.REAL, std.TEXTIO.SIDE, NATURAL, NATURAL] at vhdl_src/std/textio.vhd(138)
(explicit) TEXTIO.WRITE[std.TEXTIO.LINE, std.STANDARD.REAL, std.STANDARD.STRING] at vhdl_src/std/textio.vhd(142)
(explicit) TEXTIO.WRITE[std.TEXTIO.LINE, std.STANDARD.STRING, std.TEXTIO.SIDE, NATURAL] at vhdl_src/std/textio.vhd(145)
(explicit) TEXTIO.WRITE[std.TEXTIO.LINE, std.STANDARD.TIME, std.TEXTIO.SIDE, NATURAL, std.STANDARD.TIME] at vhdl_src/std/textio.vhd(148)
** Error: C:/Users/ssheikh/Desktop/LEMS/grlib-gpl-2020.1-b4251/lib/grlib/stdlib/testlib.vhd(443): Subprogram body for “check” has already been defined at line 386.
** Error: C:/Users/ssheikh/Desktop/LEMS/grlib-gpl-2020.1-b4251/lib/grlib/stdlib/testlib.vhd(453): (vcom-1602) Subprogram “compare” is ambiguous.
Feasible subprograms are:
(explicit) testlib.compare[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN] at C:/Users/ssheikh/Desktop/LEMS/grlib-gpl-2020.1-b4251/lib/grlib/stdlib/testlib.vhd(234)
(explicit) testlib.compare[STD_ULOGIC_VECTOR, STD_ULOGIC_VECTOR return BOOLEAN] at C:/Users/ssheikh/Desktop/LEMS/grlib-gpl-2020.1-b4251/lib/grlib/stdlib/testlib.vhd(250)
** Error: C:/Users/ssheikh/Desktop/LEMS/grlib-gpl-2020.1-b4251/lib/grlib/stdlib/testlib.vhd(583): (vcom-1602) Subprogram “compare” is ambiguous.
Feasible subprograms are:
(explicit) testlib.compare[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN] at C:/Users/ssheikh/Desktop/LEMS/grlib-gpl-2020.1-b4251/lib/grlib/stdlib/testlib.vhd(234)
(explicit) testlib.compare[STD_ULOGIC_VECTOR, STD_ULOGIC_VECTOR return BOOLEAN] at C:/Users/ssheikh/Desktop/LEMS/grlib-gpl-2020.1-b4251/lib/grlib/stdlib/testlib.vhd(250)
** Note: C:/Users/ssheikh/Desktop/LEMS/grlib-gpl-2020.1-b4251/lib/grlib/stdlib/testlib.vhd(820): VHDL Compiler exiting
End time: 16:04:24 on Mar 12,2021, Elapsed time: 0:00:00
Errors: 9, Warnings: 0
C:/modeltech_pe_2019.2/win32pe/vcom failed.
Hi,
This seems to be an issue with the VHDL standard used when compiling the files. Are you using the GRLIB script environment for building the scripts for Modelsim? Which modelsim.ini are you using?
Best regards,
Maritn
Not using the scripts. Modelsim PE 2019.2.
If you don’t use the GRLIB script environment for compilation, make sure that you compile the GRLIB files with the -93 flag, since some of the files, such as testlib.vhd, doesn’t support VHDL 2008.
Best regards,
Martin
Thanks. I think I did use the script one time and probably manually figured that out before but forgot. I am not using the LEON3 but a ColdFire V1 IP we got from Xtreme some years ago.