I am experiencing some issues with L2C lite IP, in a design where NOELV CPU (64 bits) is used. In fact, I noticed that when I select PLRU replacement mode, only 2 ways out of 4 are used (I configured L2C lite IP with 4ways, 64KB per way, 64B line). This is unexpected as the test I am executing performs numerous access to data located in the same cache set (and therefore triggers L2 replacement algorithm several time).
I know that PLRU does not perfectly mimics LRU replacement algorithm. However, I was hoping to see some data to be stored in all the 4ways of the L2 cache, at the end of test (I am executing the test in simulation, and have access to internal signals state). Yet 2 ways remained unused.
In our case we are for this time only at simulation level on Questasim. So we don’t have an Linux on board and so one.
We have try to modify the cache line from 64 to 32B, it’s not working, we really think of an issue on replacement policy as mention in another post we have done for cache L1.