GRLIB GPL 2024.4 released

General - GRLIB SoC
1

The development team is pleased to announce the release of GRLIB GPL 2024.4-b4295, which is now available for download from:

https://download.gaisler.com/products/GRLIB/bin/grlib-gpl-2024.4-b4295.tar.gz

Bitfile and netlist packages are available via:

The changelog is here:

http://download.gaisler.com/products/GRLIB/doc/Changelog.txt

and is also reproduced below.

Some of the highlights are:

NOEL-V:

  • Added option in noelvsys to include PLIC and APLIC
  • New template design for the ZCU102 board
  • Updated BF16 support
  • Updated Smrnmi implementation to support CFI
  • Numerous bug fixes and enhancements

SPIMCTRL:

  • Support for several SPI memories by means of up to 4 chip-select signals.
  • New signal to select the reset value of the extended address mode configuration.
  • ‘allow_writes’ configuration now set as register bit.

Updated example bitstreams for LEON5 and NOEL-V are available for download from:

If you find any any reproducible bugs or issues please don’t hesitate to post in the community.

----------------------- Release 2024.4-b4295 ---------------------------

2024-12-18 NOEL-V updates

  • Internal APB bus in noelvsys has been moved from 0xFC0000000 to 0xFF9000000 and some devices has been reorganized. New UART address is now 0xFF900000.
  • Added option in noelvsys to include PLIC and APLIC
  • Workaround tool issues for Design-compiler and formality
  • Added NOEL-V template design for the ZCU102 board
  • Updated BF16 support (Zfbfmin now ratified)
  • B in MISA is now set when zba, zbb, zbs are implemented
  • Improved access and fixed issues with access to IMSIC CSRs
  • Trigger update to support CBO instructions
  • Updated Smrnmi implementation to support CFI
  • Updated interrupt prioritization according to AIA
  • Removed workaround to allow 64-bit debug-module abstract command on RV32
  • CBO.inval and CBO.flush could incorrectly update the TAG and cause duplicated data tags.
  • mstatush was only available when H-extension was enabled
  • exception generated for the SSTC extension was incorrect
  • ePMP bit in mseccfg was writable when PMP was not implemented
  • updating these CSRs (menvcfgh, frm/fcsr, xtvec, stateen, mideleg/hideleg) should not be dual-issued with other instructions
  • incorrect exception when an address in a PTE failed PMA check
  • SIP.lcof was always read zero
  • sfence.w.inval and sfence.inval.ir weren’t trapping in U/VU mode and generating virtual instruction exception correctly
  • APLIC interrupt source was shifted by one bit.
  • a hit in BTB was not check to actually be a branch/jal instruction
  • SLLI >31 bit shift was not marked as illegal for RV32
  • medeleg and hedeleg to incorporate hw-fault exception
  • address translation was not enabled for the instruction following enabling MMU
  • VSATP had the same number of PPN bits as SATP and not all 41 bits of GPA could be used
  • fix for a CFI landing pad corner case
  • data cache was flushed when executing a fence instruction
  • PTE with D = 1 and A = 0 did not result in page-fault
  • LWU could be executed on RV32
  • issue with tval for mcontrol6 trigger
  • SSRDP was not checked for regarding pairing with instruction using destination
  • PMP check for hlvx and hypervisor fetch and store was incorrect (when allowed in PTE)
  • wrong fault on W-only pages with ext_zicfiss but SS disabled
  • no illegal instruction exception for sfence.vma and reading satp when supervisor mode not implemented
  • CSR stimecmp was readable when not implemented

2024-11-05 SPIMCTRL: Input signal ‘RSTADDRM’ added which can be used to select the reset value of the extended address mode configuration.

2024-10-11 SPIMCTRL: ‘allow_writes’ configuration now set as register bit. Old VHDL generic is kept and is instead used as reset value for the new register bit.

2024-10-04 SPIMCTRL: support for several SPI memories. The core now supports the use of up to four chip select signals. It can either be configured to always communicate with one out of the four devices, or instead use bit pairs from the address to select which device to use. The second approach allows a continuous view into the four memories in the SPIMCTRL ROM address region.

2

There is a question on the new version of GRLIB, which seems to be illogical, maybe it is a Vivado bug, but it really exists.

  • Build with Vivado 22.2, Linux SMP boot passed
[    1.126281] smp: Bringing up secondary CPUs ...
[    1.217520] smp: Brought up 1 node, 2 CPUs
  • Build with Vivado 24.4, Linux SMP boot failed
[    1.088258] smp: Bringing up secondary CPUs ...
[    2.220679] CPU1: failed to come online
[    2.275132] smp: Brought up 1 node, 1 CPU
  • Build with Vivado 24.4, Linux SMP boot passed, by commenting on the unused RTL port
--- grlib-gpl-2024.4-b4295/lib/gaisler/noelv/core/cpucorenv.vhd 2024-12-23 20:57:57.705135600 +0800
+++ grlib-gpl-2024.4-b4295.patch/lib/gaisler/noelv/core/cpucorenv.vhd   2025-02-05 14:57:09.405426600 +0800
@@ -780,8 +780,8 @@
       cnt           => iu_cnt,
       itracei       => itracei,
       itraceo       => itraceo,
-      pma_addr      => pma_addr,
-      pma_data      => pma_data,
+--      pma_addr      => pma_addr,
+--      pma_data      => pma_data,
       csr_mmu       => csr_mmu,
       mmu_csr       => mmu_csr,
       cap           => capability,
--- grlib-gpl-2024.4-b4295/lib/gaisler/noelv/core/iunv.vhd      2024-12-23 20:57:57.745135600 +0800
+++ grlib-gpl-2024.4-b4295.patch/lib/gaisler/noelv/core/iunv.vhd        2025-02-05 14:57:26.130338900 +0800
@@ -250,8 +250,8 @@
     cnt            : out nv_counter_out_type;  -- Perf event Out Port
     itracei        : out itrace_in_type;       -- Trace information
     itraceo        : in  itrace_out_type;      -- Trace control
-    pma_addr       : in  word64_arr;           -- PMA addresses
-    pma_data       : in  word64_arr;           -- PMA configuration
+--    pma_addr       : in  word64_arr;           -- PMA addresses
+--    pma_data       : in  word64_arr;           -- PMA configuration
     csr_mmu        : out nv_csr_out_type;      -- CSR values for MMU
     mmu_csr        : in  nv_csr_in_type;       -- CSR values for MMU
     perf           : in  std_logic_vector(31 downto 0);  -- Performance data
@@ -263,8 +263,8 @@
     testen         : in  std_ulogic;
     testrst        : in  std_ulogic
     );
-begin
-  assert pma_data'length = pma_addr'length report "PMA configuration error" severity failure;
+--begin
+--  assert pma_data'length = pma_addr'length report "PMA configuration error" severity failure;
 end;

 architecture rtl of iunv is
@@ -16593,17 +16593,17 @@
             r.x.rstate         <= dhalt;
           end if;

-          if pmaen then
-            if pma_masked = 0 then
-              -- PMA data is sanitized here.
-              r.csr.pma_data    <= pma_data_arr_create(pma_data);
-              r.csr.pma_addr    <= pma_arr_create(pma_addr);
-              r.csr.pma_precalc <= pma_precalc(pma_addr, pma_entries, physaddr);
-            else
-              -- Do not touch PMA (contains type masks).
-              r.csr.pma_data    <= pma_arr_create(pma_data);
-            end if;
-          end if;
+--          if pmaen then
+--            if pma_masked = 0 then
+--              -- PMA data is sanitized here.
+--              r.csr.pma_data    <= pma_data_arr_create(pma_data);
+--              r.csr.pma_addr    <= pma_arr_create(pma_addr);
+--              r.csr.pma_precalc <= pma_precalc(pma_addr, pma_entries, physaddr);
+--            else
+--              -- Do not touch PMA (contains type masks).
+--              r.csr.pma_data    <= pma_arr_create(pma_data);
+--            end if;
+--          end if;

           if ext_noelv = 0
           then
--- grlib-gpl-2024.4-b4295/lib/gaisler/noelv/core/noelvint.vhd  2024-12-23 20:57:57.717135600 +0800
+++ grlib-gpl-2024.4-b4295.patch/lib/gaisler/noelv/core/noelvint.vhd    2025-02-05 14:57:36.987346700 +0800
@@ -941,8 +941,8 @@
       cnt            : out nv_counter_out_type;  -- Perf event Out Port
       itracei        : out itrace_in_type;       -- Trace information
       itraceo        : in  itrace_out_type;      -- Trace control
-      pma_addr       : in  word64_arr;           -- PMA addresses
-      pma_data       : in  word64_arr;           -- PMA configuration
+--      pma_addr       : in  word64_arr;           -- PMA addresses
+--      pma_data       : in  word64_arr;           -- PMA configuration
       csr_mmu        : out nv_csr_out_type;      -- CSR values for MMU
       mmu_csr        : in  nv_csr_in_type;       -- CSR values for MMU
       perf           : in  std_logic_vector(31 downto 0);  -- Performance data