My name is Victor and it’s been a while since I wrote in this (or the previous one) community. I am using the synfifo_2p IP Core in a design. I use that block to store debug data, and then read it through amba apb. The generic abits=10 and instantiates the syncram_2p plus the ram memories of the tech I am using.
What I observed today is that the port ‘dataout’ in syncram_2p.vhd holds the data for the architecture apa3 and igloo. However, it only holds the value for one period of CLK for the architecture rtg4. This makes the syncfifo_2p ip core to only hold the dataout value for one period of clock when it is used in a rtg4. I changed my code to latch the value of the port dataout in syncfifo_2p. I wonder if there is any other generic I can set like piperead in order to avoid that situation. Shouldn’t the syncfifo_2p work equally for all the different architectures?
syncfifo_2p when fwft=0 does not currently guarantee that read data is valid for more than one cycle after you give read enable, that depends on how the RAMs behave in the underlying techmap. You could use the first-word-fallthrough mode instead (with fwft) then the output data will be held from the cycle rempty goes down up until the cycle you give the read enable and you can take as many cycles you want.
We could look at adding support for holding the read data also when fwft=0, there is already a generic to do it on the syncram_2p level (rdhold) so it should not be hard to add.
Thank you for response. I have changed the generic you mentioned and tried them in simulation and then in the FPGA. Let me give you more details about how I am using the synfifo_2p block. I am using it to store it 1024 samples coming from an ADC (abit=10). One port is connected to the ADC when strip chart telemetry is selected. Then it fills 1024 samples and an irq is enable. The syncfifo_2p read port is connected to an apb register. When a read is request from that register (my case 0c80000320) I set renable and grab the data from dataout.
Based on your reply, I changed the generic fwft=1 in order to have the first data I wrote in the fifo available in dataout. This allows me to have first data available when the apb request it. Then, I also set piperead=1. I looked at what this generic does and I do not think I need it. Then, using VUNIT and Modelsim, I fill the fifo with data and after 1024 samples, I read it using APBRead(). It works great in simulation because dataout holds the value
However, it is not reliable in the FPGA (rtg4). I do the same test, but instead using APBRead(), I run a tcl scripts in GRMON and reads 1024 times. What I can see is that periodically data sometimes is all zero. If I modify my code to latch dataout, it works great, no zeros in the data. However, the first data is lost when a read request is done thru the APB.
How do you connect the Syncfifo_2p in the APB to be read properly? As I said in the first post, apa3 and igloo do not have this problem. It is heavily dependent of the RAM blocks (not inferred).
I will try tomorrow to use the generic rhold you suggested. I do not like modifying the grlib and that generic is not passed thru syncfifo_2p.
Thanks for giving me those tips.