Hello,
I am having problems with reading SDRAM data back using SDCTRL IP targeting Zynq7000 on a ZC702. The simulation works perfectly, but lab testing is showing the data is not being read back properly. I am wondering if there are timing problems for the SDRAM data coming back. I was able to close timing using Vivado recommendations for timing constraints (setup/hold based source synchronous output delay template). Are there any recommendations or guidelines when trying to implement the SDCTRL IP on the Zynq7000?
Thanks.