How to suppress error message about PLL_TESTOUT

LEON
1

Dec 24, 2021 - I am configuring a simulation case for our original board using Artix7 for LEON3.
I encountered an error message as follows:

** Warning: (vsim-8684) No drivers exist on out port /testbench/d3/clkgen0/cgo.PLL_TESTOUT, and its initial value is not used.

Therefore, simulation behavior may occur that is not in compliance with

the VHDL standard as the initial values come from the base signal /testbendh/d3/cgo.PLL_TESTOUT

I cannot suppress this error message by “make xconfig”. I wonder how I can suppress this error message.

2

Jan 5, 2022 - PLL_TESTOUT is defined in $GRLIB/lib/techmap/gencomp/gencomp.vhd, whereas cgo.PLL_TESTOUT is not used in any sources.
I wonder what the purpose of this signal is.

Hiroki

3

9 Jan, 2022 - Even if I use leon3-minimal definitions with Xilinx (Artix7) library, I still have the following message in ModelSim.
I would appreciate if someone has a comment to suppress this warning message.

** Warning: (vsim-8683) Uninitialized out port /testbench/d3/clkgen0/xc7l/v/cgo.PLL_TESTOUT has no driver.

This port will contribute value (U) to the signal network.

** Warning: (vsim-8683) Uninitialized out port /testbench/d3/clkgen0/cgo.PLL_TESTOUT has no driver.

This port will contribute value (U) to the signal network.

Hiroki