Hi everyone,
I am currently working with GRLIB 2024.4 and the LEON3 NanoXP Medium reference design, and I have run into a timing issue that I would like to understand better.
In NanoXplore Impulse, the clock in the default example was not automatically recognized for timing constraint generation. After investigating, I noticed that the clock in the reference design is defined in picoseconds (ps), while newer versions of Impulse appear to work with constraints expressed in nanoseconds (ns). Because of this, I had to adjust the clock definition so that Impulse correctly recognizes the intended 25 MHz clock.
However, once the clock is correctly constrained, the design fails timing analysis. The worst setup slack is approximately -17.8 ns, with a reported maximum achievable frequency of only about 17 MHz.
From the timing report, the critical path appears to be somewhere within the LEON3 CPU pipeline or related downstream logic, although I have not yet fully analyzed the entire path.
Has anyone else using GRLIB 2024.4, LEON3 NanoXP Medium, and recent versions of NanoXplore Impulse observed similar behavior? Is there something specific about the intended timing setup for this reference design that I might be missing?
I can provide the full timing report if needed.
Any insights would be greatly appreciated.
Thanks!