# Problems reading data back with SDCTRL

**URL:** <https://discourse.grlib.community/t/problems-reading-data-back-with-sdctrl/619>\
**Category:** General - GRLIB SoC\
**Created:** [5 November 2026 19:24 UTC](https://discourse.grlib.community/t/problems-reading-data-back-with-sdctrl/619 "2026-11-05T19:24:35Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![davekim](https://avatars.discourse-cdn.com/v4/letter/d/54ee81/32.png) [@davekim](https://discourse.grlib.community/u/davekim)\
**Post date:** [5 November 2026 19:24 UTC](https://discourse.grlib.community/t/problems-reading-data-back-with-sdctrl/619/1 "2026-11-05T19:24:35Z")

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Hello,

I am having problems with reading SDRAM data back using SDCTRL IP targeting Zynq7000 on a ZC702. The simulation works perfectly, but lab testing is showing the data is not being read back properly. I am wondering if there are timing problems for the SDRAM data coming back. I was able to close timing using Vivado recommendations for timing constraints (setup/hold based source synchronous output delay template). Are there any recommendations or guidelines when trying to implement the SDCTRL IP on the Zynq7000?

Thanks.