# L2C lite cache IP, PLRU replacement issue

**URL:** https://discourse.grlib.community/t/l2c-lite-cache-ip-plru-replacement-issue/516
**Category:** NOEL-V
**Created:** [2 July 2025 14:48 UTC](https://discourse.grlib.community/t/l2c-lite-cache-ip-plru-replacement-issue/516 "2025-07-02T14:48:39Z")
**Posts on this page:** 1
**Showing post:** 2

<div class="post-metadata">

### Author: ![WEI](https://avatars.discourse-cdn.com/v4/letter/w/90ced4/32.png) [@WEI](https://discourse.grlib.community/u/WEI)
#### Post date: [2 July 2025 16:54 UTC](https://discourse.grlib.community/t/l2c-lite-cache-ip-plru-replacement-issue/516/2 "2025-07-02T16:54:49Z")

</div>

Can you try 32B-Line ?

I am currently using a 32B-line that successfully boots Linux, though I haven’t focused on whether only part of the ways are allocated for use.

> [@Kernel panic due to 'linesize' generic of the l2c-lite](https://discourse.grlib.community/t/kernel-panic-due-to-linesize-generic-of-the-l2c-lite/387):
>
> I tried the following combination: 1Way, 1KB/Way, 32B/Line - PASS 1Way, 32KB/Way, 32B/Line - PASS 4Way, 32KB/Way, 32B/Line - PASS 4Way, 128KB/Way, 32B/Line - PASS 4Way, 32KB/Way, 64B/Line - FAIL 4Way, 128KB/Way, 64B/Line - FAIL 32B linesize can boot kernel successfully, but 64B always fails. I tried a simple simulation and did not find any clear RTL issues. I am not sure if the problem lies in Vivado (Vivado 2022.2, XCVU19P device).

---

_[View the full topic](https://discourse.grlib.community/t/l2c-lite-cache-ip-plru-replacement-issue/516)._