# ISR not entered - BCC2

**URL:** <https://discourse.grlib.community/t/isr-not-entered-bcc2/90>\
**Category:** General - Software\
**Created:** [25 January 2021 12:55 UTC](https://discourse.grlib.community/t/isr-not-entered-bcc2/90 "2021-01-25T12:55:01Z")\
**Posts on this page:** 3\
**Page:** 1

<div class="post-metadata">

**Author:** ![flo](https://avatars.discourse-cdn.com/v4/letter/f/b38774/32.png) [@flo](https://discourse.grlib.community/u/flo)\
**Post date:** [25 January 2021 12:55 UTC](https://discourse.grlib.community/t/isr-not-entered-bcc2/90/1 "2021-01-25T12:55:01Z")

</div>

Hello,  
with the following code I try to register a ISR in core 1, which is triggered by the software of core 2 in a 3 core system.  
For some reason, the ISR is never entered, but core 1 wakes up again.  
Thanks for your help.  
-Flo

```auto
#include <stdlib.h>
#include <stdio.h>
#include <inttypes.h>

#include <bcc/bcc.h>
#include "bcc/bcc_param.h"

#define nodeprintf(...) if (1) { \
        printf("core%d:%s:%d: ", bcc_get_cpuid(), __func__ , __LINE__ ); \
        printf( __VA_ARGS__ ); \
}

void ISR (void *arg, int source) { 
        nodeprintf("This is an interrupt caused by source %d on %" PRIuPTR ". \n", source, (uintptr_t)arg);
}

int main (void)
{       
        uintptr_t id = bcc_get_cpuid();

        if (id == 0) {
            bcc_start_processor(id + 1);
            bcc_power_down();
        }
        if (id == 1) {
            void *ictx0 = bcc_isr_register(5, &ISR, (void*)id);
            if (NULL == ictx0) {
                return BCC_FAIL;
            }
            bcc_int_unmask(5);
            bcc_start_processor(id + 1);
            bcc_power_down();
            puts("Somebody woke me up.\n");
        } else {
            for (int i=0; i< 1000000; i++) {
                asm("nop");
            }
            bcc_send_interrupt(5, 1);
            bcc_power_down(); // schlafen
        }
        
        return 0;
}

```

---

<div class="post-metadata">

**Author:** ![Moritz](https://avatars.discourse-cdn.com/v4/letter/m/58956e/32.png) [@Moritz](https://discourse.grlib.community/u/Moritz)\
**Post date:** [17 March 2022 09:33 UTC](https://discourse.grlib.community/t/isr-not-entered-bcc2/90/2 "2022-03-17T09:33:54Z")

</div>

Hey Flo, I ran into the same issue! After some testing it seems to me like the cores do not execute ISRs when woken up from sleep mode. If an interrupt is triggered while the core is awake ISRs work as expected for me.  
Best regards  
Moritz

---

<div class="post-metadata">

**Author:** ![mhjorth](https://avatars.discourse-cdn.com/v4/letter/m/3ec8ea/32.png) [@mhjorth](https://discourse.grlib.community/u/mhjorth)\
**Post date:** [21 March 2022 09:29 UTC](https://discourse.grlib.community/t/isr-not-entered-bcc2/90/3 "2022-03-21T09:29:39Z")

</div>

Hi Flo and Moritz!

Sorry for not answering this thread earlier. These BCC2 features are for AMP operation, are you building this properly as an AMP application? You need to split up the memory space between the CPUs, create a separate binary with different load address for each CPU and then have a separate stack for each CPU so the processors don’t touch each other’s memory. BCC2 is not designed for SMP operation, if you try to run it as an SMP application (i.e load one copy boot all CPUs from the same address) the different CPUs will write over each other and you get strange effects. You will have to use some OS that is designed for SMP operation like RTEMS-SMP or Linux if you want to do that.