# How to suppress error message about PLL\_TESTOUT

**URL:** <https://discourse.grlib.community/t/how-to-suppress-error-message-about-pll-testout/217>\
**Category:** LEON\
**Created:** [24 December 2021 12:51 UTC](https://discourse.grlib.community/t/how-to-suppress-error-message-about-pll-testout/217 "2021-12-24T12:51:47Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![Hihara](https://avatars.discourse-cdn.com/v4/letter/h/ecae2f/32.png) [@Hihara](https://discourse.grlib.community/u/Hihara)\
**Post date:** [24 December 2021 12:51 UTC](https://discourse.grlib.community/t/how-to-suppress-error-message-about-pll-testout/217/1 "2021-12-24T12:51:47Z")

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Dec 24, 2021 - I am configuring a simulation case for our original board using Artix7 for LEON3.  
I encountered an error message as follows:

# \*\* Warning: (vsim-8684) No drivers exist on out port /testbench/d3/clkgen0/cgo.PLL\_TESTOUT, and its initial value is not used.

# Therefore, simulation behavior may occur that is not in compliance with

# the VHDL standard as the initial values come from the base signal /testbendh/d3/cgo.PLL\_TESTOUT

I cannot suppress this error message by “make xconfig”. I wonder how I can suppress this error message.

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**Author:** ![Hihara](https://avatars.discourse-cdn.com/v4/letter/h/ecae2f/32.png) [@Hihara](https://discourse.grlib.community/u/Hihara)\
**Post date:** [5 January 2022 12:13 UTC](https://discourse.grlib.community/t/how-to-suppress-error-message-about-pll-testout/217/2 "2022-01-05T12:13:34Z")

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Jan 5, 2022 - PLL\_TESTOUT is defined in $GRLIB/lib/techmap/gencomp/gencomp.vhd, whereas cgo.PLL\_TESTOUT is not used in any sources.  
I wonder what the purpose of this signal is.

Hiroki

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**Author:** ![Hihara](https://avatars.discourse-cdn.com/v4/letter/h/ecae2f/32.png) [@Hihara](https://discourse.grlib.community/u/Hihara)\
**Post date:** [8 January 2022 19:10 UTC](https://discourse.grlib.community/t/how-to-suppress-error-message-about-pll-testout/217/3 "2022-01-08T19:10:54Z")

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9 Jan, 2022 - Even if I use leon3-minimal definitions with Xilinx (Artix7) library, I still have the following message in ModelSim.  
I would appreciate if someone has a comment to suppress this warning message.

# \*\* Warning: (vsim-8683) Uninitialized out port /testbench/d3/clkgen0/xc7l/v/cgo.PLL\_TESTOUT has no driver.

# This port will contribute value (U) to the signal network.

# \*\* Warning: (vsim-8683) Uninitialized out port /testbench/d3/clkgen0/cgo.PLL\_TESTOUT has no driver.

# This port will contribute value (U) to the signal network.

Hiroki