# GRLIB GPL 2026.2 released

**URL:** <https://discourse.grlib.community/t/grlib-gpl-2026-2-released/576>\
**Category:** General - GRLIB SoC\
**Created:** [1 July 2026 11:58 UTC](https://discourse.grlib.community/t/grlib-gpl-2026-2-released/576 "2026-07-01T11:58:27Z")\
**Posts on this page:** 1\
**Page:** 1

<div class="post-metadata">

**Author:** ![joaquin.espana](https://avatars.discourse-cdn.com/v4/letter/j/3da27b/32.png) [@joaquin.espana](https://discourse.grlib.community/u/joaquin.espana)\
**Post date:** [1 July 2026 11:58 UTC](https://discourse.grlib.community/t/grlib-gpl-2026-2-released/576/1 "2026-07-01T11:58:27Z")

</div>

The development team is pleased to announce the release of GRLIB GPL 2026.2-b4300, which is now available for download from:

[https://download.gaisler.com/products/GRLIB/bin/grlib-gpl-2026.2-b4300.tar.gz](https://download.gaisler.com/products/GRLIB/bin/grlib-gpl-2026.2-b4300.tar.gz)

Bitfile and netlist packages are available via:

> **[GRLIB IP Library | Gaisler](https://www.gaisler.com/grlib-ip-library)**
>
> Find FAQs and support resources and download & explore the GRLIB GPL version, including source code, manuals, and FPGA bitfiles.

The changelog is here:

[http://download.gaisler.com/products/GRLIB/doc/Changelog.txt](http://download.gaisler.com/products/GRLIB/doc/Changelog.txt)

and is also reproduced below.

Some of the highlights are:

- Multiple new features, fixes and updates to NOEL-V
- Fixes to the AXI to AHB bridges
- Little-endian support added to several IPs
- New revision of SPIMCTRL with new registers and fixes
- Minor fixes to L2C\_LITE and APBUART

Updated example bitstreams for LEON5 and NOEL-V are available for download from:

> **[LEON FPGA examples - LEON SPARC Processors | Gaisler](https://www.gaisler.com/secondary-product-category/leon-sparc-processors#LEON-FPGA-examples)**
>
> The LEON3 processor offers robust fault tolerance and performance for space and high-reliability applications, including satellites and scientific instruments. | Explore LEON processors for space applications. Benefit from a robust software ecosystem...

> **[NOEL FPGA examples - NOEL RISC-V Processors | Gaisler](https://www.gaisler.com/secondary-product-category/noel-risc-v-processors#NOEL-FPGA-examples)**
>
> The NOEL3 is a configurable RISC-V processor IP core, described in VHDL. The architecture is designed to utilize a small area footprint and to maintain execution time predictability. | NOEL processors provide reliable performance, flexibility, and...

If you find any any reproducible bugs or issues please don’t hesitate to post in the community.

----------------------- Release 2026.2-b4300 ---------------------------

2026-06-30 noelv-digilent-arty-a7 design: default NOEL-V configuration changed to MC as the GP configuration no longer fits in the device.

2026-06-19 NOEL-V: Currently only supporting cmemconf = 2

- Data cache tag configuration: 2 - two single port memories, valid bits in flip flops

2026-06-17 Status register read command added for the simulation SPI memory model (ftype=4 only)

2026-06-15 SPICTRL: Expand documentation of CMD.LST behaviour

2026-06-09 SPIMCTRL: Bugfix for register access while SPLIT in progress Fixed a bug where if a flash memory access was currently being processed with a SPLIT response, and another AHB master sent a register access to the SPIMCTRL, then that register access could affect the flash memory access and corrupt it.

2026-06-05 Asynchronous reset support added to IRQMP

2026-05-27 L2C\_LITE: Updated the PLRU state behaviour by updating the parent nodes only after moving upward in the tree,instead of overwriting the same node twice.

2026-05-19 NOEL-V updates:

- Bump version to 3
- Added AHB bus error register
- Debug-module, Changed PnP offset to 32 for debug link masters and debug module
- Debug\_module, implemented relaxedpriv and updated to version 1.0 of the spec

2026-04-21 AXI2AHB: Fix stall after HGRANT and HREADY loss

2026-04-17 AXI2AHB: Feature addition and bug fix The bridge now tries to perform AHB bursts rather than only single transactions. A bug with stale pipeline data causing data loss during early HGRANT loss has been fixed.

2026-04-16 NOEL-V updates:

- Added random replacement policy
- Update CBO to operate on 64 bytes and fix permission checks
- Added ARCHID and IMPLID
- Reorganize NOELV config files (custom CPU config, PMA)
- Increase number of PMP entries to 16 for HP
- Debug-module, DPC can now we read while hart is running
- Update write combining feature
- Added support for “breakpoint only” MCONTROL triggers
- Update NOEL-V HP to support 24 TLBs
- HPM updates
- Fixed corner case for permission checks for atomics
- Update to clock-gating due to WFI
- Removed option for cache freese and TLB disable
- Debug-module, Update to havereset, external break
- Update for asynchronous reset

2026-04-15 APBUART: Added combined APBUART and APBUART16550

2026-03-20 AXI: New component AXI2APB, refactored extended AXI types

2026-03-17 Asynchronous reset support added to GRGPIO, GPTIMER and I2CMST

2026-03-16 AHB2AHB: little-endian support added

2026-03-14 NOEL-V updates:

- Fixed issue with diagnostic data-tag write
- Fix RAW/WAW issue with mcounteren and scountinhibit
- Move ACLINT and L2C register interface to 0xB000’0000 and 0xB100’0000. Both devices need a PMA region that is set to widebus to be able to do 64-bit accesses.
- Triggers:
- Update how unaligned triggers are handled.
- Fix trigger behavior with respect to CBO operations.
- Add actions 2 and 3 to triggers
- Add custom capability CSRs to help software avoid probing for implemented extensions/features. See docs for exact layout.
- Remove custom instructions diag.(s/l).(d/s/i)ct. Replaced with diag.(l/s).xtag, see docs for usage.
- Disable 32-bit diagnostic access on RV64, diag.(l/s)d are backwards compatible.
- Diagnostic store instructions that try modify read-only state now throw illegal.
- Fix various MMU/PMA bugs
- Enable possibility to do write combining by making CSR cctrl(14) writeable. This will allow contiguous 64-bit writes to be combined into 128-bit accesses.
- Implement extensions: Svnapot, Smcntrpmf, Svrsw60t59b
- Implement unratified extension Smpmpmt (disabled in CSR features)
- Fix FPU bugs regarding fmvp.d.x and int → float conversions
- Disable Smepmp in cfg 2 since it doesn’t have any PMP entries
- Added shlcofideleg and smcdeleg extension
- Update to CSR handling
- APLIC: base\_ppn field was not shifted 12 bits to the left to calculate the IMSIC base address.
- Fix to not update m/htinst on shadowstack push/pop exceptions
- The double-trap extension (smdbltr and ssdbltrp) have been updated to version 1.0.
- Interrupt was not masked when executing in the program buffer
- Added support for external instruction trace
- Memory regins could not be defined uncacheable for instructions
- Load-reserved (LR) was not working for uncaicheable memory.
- Updated support for asynchronous reset
- Update for MTIME implementation

2026-03-12 AXI: New components REGISTER\_SLICE, AXI4\_REGISTER\_SLICE and AXI4DEMUX.

2026-03-09 LEON5SYS: Corrected reset values for DBPM, CF, CS, and DWT in GRIP documentation.

2026-03-06 DBGMST: Added new debug AHB master core New core providing a master interface capable of generating arbitrary bus accesses controlled through an APB register interface. Exposes a generic\_bm interface and is useful when debugging bus bridges within a design. Currently only AHB variants are implemented.

2026-02-18 AXI:

- New components ARBITER\_TREE and AXI4MUX.
- Added support for extended address and ID widths.
- Force output address alignment in AXI4\_RESIZE.

2026-02-02 New NOEL-V template design for Versal targeting ADM-PA100.

2026-01-13 LEON5: Fix bug in ASI22 cross-CPU IPI/flush functionality

2026-01-13 LEON5: Fix several issues when using atomic instructions (SWAP/LDSTUB/CASA) to an address in Data TCM.

2026-01-12 AHB2AXIB:

- Updated endianness handling. Added support for ahb record endian signal when ahb\_endianness generic is set to 2.
- Fix narrow burst address inversion.

2025-12-04 SPIMCTRL: Updated to revision 5

- Added support for EDAC (only in GRLIB-FT distributions).
- Added read-only register for readout of the value of the offset-generic.
- Added writeable address offset/paging register.
- Added asynchronous reset bypass for all I/O.
- Added option to set reset values of read opcode, offset register, EDAC, chip-select, and number of dummy bytes.
- Added option for programmable scaler of configurable length.
- Fixed a bug that caused short low pulses (two system clocks) on spio.sck.

2025-10-14 AXI2AHB: Fix issue in read backpressure handling

2025-09-22 APBUART: Fix break character detection range

- Corrected minimum break character length from 10 to 11 bits to prevent false detection of normal UART frames (start + 8 data + optional parity + stop)
- Updated transmitter to send minimum 11 consecutive zeroes

2025-09-02 L2C-Lite: Fixed functionality of the ‘dw\_bw’ generic. Previously the generic was tied to the buswidth of the AHB system, now it is possible to set it to a smaller value as well.

2025-08-15 AXI2AHB: Fix hgrant loss handling during transactions