# GRLIB GPL 2025.2 released

**URL:** <https://discourse.grlib.community/t/grlib-gpl-2025-2-released/518>\
**Category:** General - GRLIB SoC\
**Created:** [4 July 2025 13:11 UTC](https://discourse.grlib.community/t/grlib-gpl-2025-2-released/518 "2025-07-04T13:11:04Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![joaquin.espana](https://avatars.discourse-cdn.com/v4/letter/j/3da27b/32.png) [@joaquin.espana](https://discourse.grlib.community/u/joaquin.espana)\
**Post date:** [4 July 2025 13:11 UTC](https://discourse.grlib.community/t/grlib-gpl-2025-2-released/518/1 "2025-07-04T13:11:04Z")

</div>

The development team is pleased to announce the release of GRLIB GPL 2025.2-b4298, which is now available for download from:

[https://download.gaisler.com/products/GRLIB/bin/grlib-gpl-2025.2-b4298.tar.gz](https://download.gaisler.com/products/GRLIB/bin/grlib-gpl-2025.2-b4298.tar.gz)

Bitfile and netlist packages are available via:

> **[GRLIB IP Library | Gaisler](https://www.gaisler.com/grlib-ip-library)**
>
> Find FAQs and support resources and download & explore the GRLIB GPL version, including source code, manuals, and FPGA bitfiles.

The changelog is here:

[http://download.gaisler.com/products/GRLIB/doc/Changelog.txt](http://download.gaisler.com/products/GRLIB/doc/Changelog.txt)

and is also reproduced below.

Some of the highlights are:

- NOEL-V: new features and fixes including
  - Added shlcofideleg and smcdeleg extension
  - Added support for Svnapot extension and Sv48
  - The double-trap extension (smdbltr and ssdbltrp) has been updated version 1.0

- APBUART: support for break characters in both transmission and reception
- Design systests migrated to BCC2 to remove existing dependency on BCC1
- Minor fixes and updates for the following IPs:
  - LEON5 fixes in DTCM and LDSTUB/LDSTUBA opcode check
  - GRDMAC2
  - AXI2AHB
  - GRGPIO

Updated example bitstreams for LEON5 and NOEL-V are available for download from:

> **[LEON SPARC Processors | Gaisler](https://www.gaisler.com/secondary-product-category/leon-sparc-processors#LEON-FPGA-examples)**
>
> Explore LEON processors for space applications. Benefit from a robust software ecosystem and a legacy of proven reliability.

> **[NOEL RISC-V Processors | Gaisler](https://www.gaisler.com/secondary-product-category/noel-risc-v-processors#NOEL-FPGA-examples)**
>
> NOEL processors provide reliable performance, flexibility, and robustness, ensuring mission success and high reliability in space and critical applications

If you find any any reproducible bugs or issues please don’t hesitate to post in the community.

----------------------- Release 2025.2-b4298 ---------------------------

2025-06-30 NOEL-V updates:

- Update interrupt port definition (new record type)
- Prevent H-extension to be enabled for RV32 (currently not supported)
- MC standard configuration has been updated to increase L1 to 4-way and remove double-precision floating-point (only supporting F extension)
- The double-trap extension (smdbltr and ssdbltrp) have been updated version 1.0
- Update to CSR handling (illegal checks, and exceptions)
- Added shlcofideleg and smcdeleg extension
- Added SVADU extension
- PLIC now supports more then 31 interrupt sources
- Custom FEATURE CSR updated (bits has been redefined)
- Added support for Svnapot extension and Sv48
- Update illegal checks for CBO instructions
- APLIC: base\_ppn field was not shifted 12 bits to the left to calculate the IMSIC base address.
- G-stage access fault was raised instead of page fault for some cases
- Fixed issue with PMA/PMP check during page-walk
- Fix to not update m/htinst on shadowstack push/pop exceptions
- Fixed incorrect fault for CFI landing pad faults
- Executing ssamoswap in machine mode was not handled correctly
- Update Smstateen extension to incorporate the bits p1p13 & C.
- Modify write behavior of bits in hstateen/sstateen, if mstateen.bit is 0 then hstateen.bit/sstateen.bit is no longer writeable and previous bits are preserved.
- Update envcfg to incorporate read-only behavior for bits not set in higher privilege mode envcfg. Example) if menvcfg.sse = 0 =\> RO (s/h)envcfg.sse. Previous bits preserved.
- Update CBO and ssamoswap exception behavior, these instructions could previously throw a virtual instruction exception even if its menvcfg bit was 0.

2025-06-25 TECHMAP: Add UltraScale/UltraScale-Plus mapping for DDR\_OREG

2025-06-24 AHB2AXIB: new generic to support AMBA address widths of more than 32 bits (not compatible yet with PnP scanning).

2025-06-17 APBUART: Added break character support

- Increased APBUART revision to 2
- Updated the core to support transmission and detection of break characters within a configurable range of 10-16 zeroes. Break operation is managed via the control register of the apb bus.
- Enabled break handling in loop-back operation
- Added a capability register that reports the values for certain RTL instantiation generics, including FIFO size and flow
- The debug bit in the control register is now read-only. Read/write access for debug functionality has been relocated to the FIFO debug control register.

2025-06-16 GRGPIO: Added set and clear register support to facilitate atomic accesses to selected registers.

2025-06-10 BCC: BCC1 to BCC2 migration

- Affects systest in designs directory

2025-06-09 LEON5: Fix issue on LDSTUB/LDSTUBA opcode check

2025-05-23 LEON5: DTCM Fixes

- Fix an issue where ASI accesses where triggering unwanted dtcmhit.

2025-04-16 AXI2AHB: fix simultaneous read and write accesses

2025-04-03 GRDMAC2: Incorrect calculation of the burst\_chop\_mask generic value in generic\_bm instantiation is fixed. generic\_bm\_ahb instantiation in the grdmac2 has the default value 1024 for burst\_chop\_mask generic.