# GRETH/EDCL debug link report error under NOELV design

**URL:** <https://discourse.grlib.community/t/greth-edcl-debug-link-report-error-under-noelv-design/271>\
**Category:** NOEL-V\
**Created:** [31 August 2022 02:45 UTC](https://discourse.grlib.community/t/greth-edcl-debug-link-report-error-under-noelv-design/271 "2022-08-31T02:45:26Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![WEI](https://avatars.discourse-cdn.com/v4/letter/w/90ced4/32.png) [@WEI](https://discourse.grlib.community/u/WEI)\
**Post date:** [31 August 2022 02:45 UTC](https://discourse.grlib.community/t/greth-edcl-debug-link-report-error-under-noelv-design/271/1 "2022-08-31T02:45:26Z")

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Hello,

I ported leon3mp and noelv-generic template designs to my FPGA board.

- LEON3 design: Both AHBUART and GRETH/EDCL debug link work fine

- NOELV design: The AHBUART works, but GRETH/EDCL will report an error

The same NOELV design, since AHBUART works, it seems that the problem is not ‘GRLIB IP cores that are not distributed under GPL license’.

Would somebody have any suggestions, Thanks.

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**Author:** ![WEI](https://avatars.discourse-cdn.com/v4/letter/w/90ced4/32.png) [@WEI](https://discourse.grlib.community/u/WEI)\
**Post date:** [3 September 2022 17:25 UTC](https://discourse.grlib.community/t/greth-edcl-debug-link-report-error-under-noelv-design/271/2 "2022-09-03T17:25:57Z")

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In the NOELV base design, GRMON scans PnP information in the big endian by default, while EDCL works in the little endian mode.

I wonder if this is the problem ?