# Error compiling NOEL-V with Modelsim

**URL:** <https://discourse.grlib.community/t/error-compiling-noel-v-with-modelsim/91>\
**Category:** NOEL-V\
**Created:** [2 February 2021 14:24 UTC](https://discourse.grlib.community/t/error-compiling-noel-v-with-modelsim/91 "2021-02-02T14:24:41Z")\
**Posts on this page:** 11\
**Page:** 1

<div class="post-metadata">

**Author:** ![Michele](https://avatars.discourse-cdn.com/v4/letter/m/ed8c4c/32.png) [@Michele](https://discourse.grlib.community/u/Michele)\
**Post date:** [2 February 2021 14:24 UTC](https://discourse.grlib.community/t/error-compiling-noel-v-with-modelsim/91/1 "2021-02-02T14:24:41Z")

</div>

Hello,  
I am coming back to grlib after several years to try NOEL-V, but I cannot get it to work. Here are my steps:

- I go to ./design/noelv-xilinx-vc707
- Following README, I first issue “make map\_xilinx\_7series\_lib” compilation is fine with no error
- I then try “make sim” and I get this error:  
vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/unisim/memory\_ultrascale.vhd  
\*\* Error: (vcom-11) Could not find unisim.vcomponents.

###### …/…/lib/techmap/unisim/memory\_ultrascale.vhd(33): use UNISIM.vcomponents.all;

\*\* Error (suppressible): …/…/lib/techmap/unisim/memory\_ultrascale.vhd(33): (vcom-1195) Cannot find expanded name “unisim.vcomponents”.  
\*\* Error: …/…/lib/techmap/unisim/memory\_ultrascale.vhd(33): Unknown expanded name.

###### …/…/lib/techmap/unisim/memory\_ultrascale.vhd(38): entity ultrascale\_syncram is

\*\* Error: …/…/lib/techmap/unisim/memory\_ultrascale.vhd(38): VHDL Compiler exiting  
make[2]: \*\*\* [vsim] Error 2  
make[2]: Leaving directory `/calcul/gailser/grlib-gpl-2020.4-b4261/designs/noelv-xilinx-vc707' make[1]: *** [make.work] Error 2 make[1]: Leaving directory `/calcul/gailser/grlib-gpl-2020.4-b4261/designs/noelv-xilinx-vc707’  
make: \*\*\* [sim] Error 2

I am using modelsim 10.4 and Vivado 2018.1

I tried to use compiling from another noel-V design and I get the same error. Any ideas?

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<div class="post-metadata">

**Author:** ![salmanisheikh](https://avatars.discourse-cdn.com/v4/letter/s/8dc957/32.png) [@salmanisheikh](https://discourse.grlib.community/u/salmanisheikh)\
**Post date:** [2 February 2021 17:31 UTC](https://discourse.grlib.community/t/error-compiling-noel-v-with-modelsim/91/2 "2021-02-02T17:31:48Z")

</div>

It seems the unisim library needs to be created and compiled from your Vivado. The source files are here for my Vivado 2020.1:

C:\Xilinx\Vivado\2020.1\data\vhdl\src

Not sure if the script compiles those for you or you have to manually do that step.

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<div class="post-metadata">

**Author:** ![ronnback](https://avatars.discourse-cdn.com/v4/letter/r/f17d59/32.png) [@ronnback](https://discourse.grlib.community/u/ronnback)\
**Post date:** [3 February 2021 14:07 UTC](https://discourse.grlib.community/t/error-compiling-noel-v-with-modelsim/91/3 "2021-02-03T14:07:10Z")

</div>

Hi,

I can’t reproduce the error at my end. map\_xilinx\_7series\_lib uses Vivado to compile the Xilinx libraries - among others the unisim library - and maps them in modelsim.ini, so that the simulator can find them. The libraries are compiled to ./xilinx\_lib/ so you should be able to find a unisim directory there. Can you please post the output from map\_xilinx\_7series\_lib, so that we can check them.

Best regards,  
Martin

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<div class="post-metadata">

**Author:** ![Michele](https://avatars.discourse-cdn.com/v4/letter/m/ed8c4c/32.png) [@Michele](https://discourse.grlib.community/u/Michele)\
**Post date:** [3 February 2021 15:06 UTC](https://discourse.grlib.community/t/error-compiling-noel-v-with-modelsim/91/4 "2021-02-03T15:06:37Z")

</div>

Hi, here is the output I get starting after a distclean:

> xph2slempo@cimepe36:/calcul/gailser/grlib-gpl-2020.4-b4261/designs/noelv-xilinx-vc707$ make map\_xilinx\_7series\_lib  
> GRLIB settings:  
> GRLIB = …/…  
> GRLIB\_CONFIG = noelv\_config.vhd  
> GRLIB\_SIMULATOR = ModelSim  
> TECHLIBS setting = unisim  
> Top-level design = noelvmp  
> Simulation top-level = testbench  
> Scanning libraries:  
> grlib: stdlib util sparc riscv modgen amba dftlib  
> techmap: gencomp alltech inferred unisim maps  
> eth: comp core wrapper  
> opencores: can i2c ge\_1000baseX  
> gaisler: arith memctrl srmmu leon3 leon3v3 leon4 l2cache/pkg can axi misc net uart sim jtag greth usb ddr i2c spi subsys noelv pl ic noelv/subsys leon5 leon5v0  
> work: debug
> 
> \*\*\*\*\*\* Vivado v2018.1 (64-bit)  
> \*\*\*\* SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018  
> \*\*\*\* IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018  
> \*\* Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
> 
> source ./xilinx\_lib/noelvmp\_simlib.tcl
> 
> # compile\_simlib -quiet -directory ./xilinx\_lib/ -family all -language all -simulator modelsim -library unisim -library simprim
> 
> INFO: [Common 17-206] Exiting Vivado at Wed Feb 3 16:02:19 2021…  
> Model Technology ModelSim SE-64 vmap 10.4 Lib Mapping Utility 2014.12 Dec 2 2014  
> vmap secureip\_ver ./xilinx\_lib/secureip  
> Modifying modelsim.ini  
> Model Technology ModelSim SE-64 vmap 10.4 Lib Mapping Utility 2014.12 Dec 2 2014  
> vmap secureip ./xilinx\_lib/secureip  
> Modifying modelsim.ini  
> Model Technology ModelSim SE-64 vmap 10.4 Lib Mapping Utility 2014.12 Dec 2 2014  
> vmap axi\_bfm ./xilinx\_lib/secureip  
> Modifying modelsim.ini  
> Model Technology ModelSim SE-64 vmap 10.4 Lib Mapping Utility 2014.12 Dec 2 2014  
> vmap unisims\_ver ./xilinx\_lib/unisims\_ver  
> Modifying modelsim.ini  
> Model Technology ModelSim SE-64 vmap 10.4 Lib Mapping Utility 2014.12 Dec 2 2014  
> vmap unisim ./xilinx\_lib/unisim  
> Modifying modelsim.ini  
> Model Technology ModelSim SE-64 vmap 10.4 Lib Mapping Utility 2014.12 Dec 2 2014  
> vmap unimacro\_ver ./xilinx\_lib/unimacro\_ver  
> Modifying modelsim.ini  
> Model Technology ModelSim SE-64 vmap 10.4 Lib Mapping Utility 2014.12 Dec 2 2014  
> vmap unimacro ./xilinx\_lib/unimacro  
> Modifying modelsim.ini  
> Model Technology ModelSim SE-64 vmap 10.4 Lib Mapping Utility 2014.12 Dec 2 2014  
> vmap simprim\_ver ./xilinx\_lib/simprims\_ver  
> Modifying modelsim.ini  
> Model Technology ModelSim SE-64 vmap 10.4 Lib Mapping Utility 2014.12 Dec 2 2014  
> vmap unifast\_ver ./xilinx\_lib/unifast\_ver  
> Modifying modelsim.ini  
> Model Technology ModelSim SE-64 vmap 10.4 Lib Mapping Utility 2014.12 Dec 2 2014  
> vmap unifast ./xilinx\_lib/unifast\_ver  
> Modifying modelsim.ini

> xph2slempo@cimepe36:/calcul/gailser/grlib-gpl-2020.4-b4261/designs/noelv-xilinx-vc707$ make sim  
> make vsim  
> make[1]: Entering directory `/calcul/gailser/grlib-gpl-2020.4-b4261/designs/noelv-xilinx-vc707’  
> Reading pref.tcl
> 
> # 10.4
> 
> # do libs.do
> 
> # quit
> 
> make[2]: Entering directory `/calcul/gailser/grlib-gpl-2020.4-b4261/designs/noelv-xilinx-vc707’  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/stdlib/version.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/stdlib/config\_types.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib noelv\_config.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/stdlib/stdlib.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/stdlib/stdio.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/stdlib/testlib.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/util/util.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/sparc/sparc.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/sparc/sparc\_disas.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/sparc/cpu\_disas.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/riscv/riscv.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/riscv/riscv\_disas.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/riscv/cpu\_disas.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/modgen/multlib.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/modgen/leaves.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/amba.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/devices.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/defmst.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/apbctrl.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/apbctrlx.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/apbctrldp.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/apbctrlsp.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/ahbctrl.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/dma2ahb\_pkg.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/dma2ahb.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/ahbmst.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/ahblitm2ahbm.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/dma2ahb\_tp.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/amba/amba\_tp.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/dftlib/dftlib.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/dftlib/trstmux.vhd  
> vcom -quiet -explicit -O0 -93 -work grlib …/…/lib/grlib/dftlib/synciotest.vhd  
> vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/gencomp/gencomp.vhd  
> vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/gencomp/netcomp.vhd  
> vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/alltech/allclkgen.vhd  
> vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/alltech/allddr.vhd  
> vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/alltech/allmem.vhd  
> vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/alltech/allmul.vhd  
> vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/alltech/allpads.vhd  
> vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/alltech/alltap.vhd  
> vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/inferred/memory\_inferred.vhd  
> vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/inferred/ddr\_inferred.vhd  
> vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/inferred/mul\_inferred.vhd  
> vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/inferred/ddr\_phy\_inferred.vhd  
> vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/inferred/ddrphy\_datapath.vhd  
> vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/inferred/fifo\_inferred.vhd  
> vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/inferred/sim\_pll.vhd  
> vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/inferred/lpddr2\_phy\_inferred.vhd  
> vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/unisim/memory\_kintex7.vhd  
> vcom -quiet -explicit -O0 -93 -work techmap …/…/lib/techmap/unisim/memory\_ultrascale.vhd  
> \*\* Error: (vcom-11) Could not find unisim.vcomponents.
> 
> ###### …/…/lib/techmap/unisim/memory\_ultrascale.vhd(33): use UNISIM.vcomponents.all;
> 
> \*\* Error (suppressible): …/…/lib/techmap/unisim/memory\_ultrascale.vhd(33): (vcom-1195) Cannot find expanded name “unisim.vcomponents”.  
> \*\* Error: …/…/lib/techmap/unisim/memory\_ultrascale.vhd(33): Unknown expanded name.
> 
> ###### …/…/lib/techmap/unisim/memory\_ultrascale.vhd(38): entity ultrascale\_syncram is
> 
> \*\* Error: …/…/lib/techmap/unisim/memory\_ultrascale.vhd(38): VHDL Compiler exiting  
> make[2]: \*\*\* [vsim] Error 2  
> make[2]: Leaving directory `/calcul/gailser/grlib-gpl-2020.4-b4261/designs/noelv-xilinx-vc707' make[1]: *** [make.work] Error 2 make[1]: Leaving directory `/calcul/gailser

I tried compiling manually vcomponents:  
vcom /softslin/vivado\_18.1/Vivado/2018.1/data/vhdl/src/unisims/unisim\_VCOMP.vhd -work unisim  
Bit it just shifts the issue: after it still cannot find the RAMBxx components inside VCOMP

Regards,  
Michele

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<div class="post-metadata">

**Author:** ![ronnback](https://avatars.discourse-cdn.com/v4/letter/r/f17d59/32.png) [@ronnback](https://discourse.grlib.community/u/ronnback)\
**Post date:** [3 February 2021 15:50 UTC](https://discourse.grlib.community/t/error-compiling-noel-v-with-modelsim/91/5 "2021-02-03T15:50:01Z")

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Hi Michele,

Thank you! I now realized I used another version of Modelsim than you and when I switch to Modelsim 10.4 I get the same error. Do you have access to a newer version of Modelsim? I tried with 10.6a without getting an error.

Best regards,  
Martin

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<div class="post-metadata">

**Author:** ![ronnback](https://avatars.discourse-cdn.com/v4/letter/r/f17d59/32.png) [@ronnback](https://discourse.grlib.community/u/ronnback)\
**Post date:** [3 February 2021 16:17 UTC](https://discourse.grlib.community/t/error-compiling-noel-v-with-modelsim/91/6 "2021-02-03T16:17:37Z")

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The script used for compiling the Xilinx libraries have the -quiet flag set, which removes most of the output. If one mimics what the script environment does without the quiet flag, Vivado gives the following warning:

WARNING: [Vivado 12-5495] Detected incompatible modelsim simulator installation version ‘10.4’! The supported simulator version for the current Vivado release is ‘10.6c’.

The release notes of Vivado 2018.1 lists Modelsim 10.6c as the compatible version, so it’s possible that something doesn’t work as expected when compiling for 10.4, but since the libraries are created by Vivado, the GRLIB script environment doesn’t detect the incompatibility.

Best regards,  
Martin

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<div class="post-metadata">

**Author:** ![Michele](https://avatars.discourse-cdn.com/v4/letter/m/ed8c4c/32.png) [@Michele](https://discourse.grlib.community/u/Michele)\
**Post date:** [3 February 2021 18:17 UTC](https://discourse.grlib.community/t/error-compiling-noel-v-with-modelsim/91/7 "2021-02-03T18:17:13Z")

</div>

I did not know about this incompatibility, thanks for finding out!  
The more recent version we have is 10.5 and it is still incompatible, I will ask for a newer version to be installed.  
BTW, is there a possibility to simulate the Noel-V using only generic technology to remove dependency to unisim?

Thanks,

Michele

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<div class="post-metadata">

**Author:** ![ronnback](https://avatars.discourse-cdn.com/v4/letter/r/f17d59/32.png) [@ronnback](https://discourse.grlib.community/u/ronnback)\
**Post date:** [4 February 2021 07:26 UTC](https://discourse.grlib.community/t/error-compiling-noel-v-with-modelsim/91/8 "2021-02-04T07:26:24Z")

</div>

NOEL-V is possible to simulate without technology dependencies, but the current NOEL-V template designs target Xilinx FPGAs.

Best regards,  
Martin

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<div class="post-metadata">

**Author:** ![Michele](https://avatars.discourse-cdn.com/v4/letter/m/ed8c4c/32.png) [@Michele](https://discourse.grlib.community/u/Michele)\
**Post date:** [5 February 2021 10:04 UTC](https://discourse.grlib.community/t/error-compiling-noel-v-with-modelsim/91/9 "2021-02-05T10:04:31Z")

</div>

I have been trying all combinations of tools, I cannot get it to work.

- my admin installed 10.6.c, but is Questasim, not Modelsim. Apparently it changed denomination after 10.5
- I can get the simulation to start, but I immediately get an “IU in Error Mode”.
- I followed all steps, cannot really understand what I am doing wrong.

Quite a pity there is not a simple “generic” testbench just for simulation. It was one of the strong points of all Leon2: you could get it up and running really fast and then start minding about FPGA…

I took detailed logs of all the steps, I put them on a file sender to avoid clogging up the forum.

[Compilation and Simulation logs](https://filesender.renater.fr/?s=download&token=a42ddc82-5bc5-4021-9b2e-b734669989c9)

Any idea where it gets wrong?

Thanks,  
Michele

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<div class="post-metadata">

**Author:** ![nils](https://avatars.discourse-cdn.com/v4/letter/n/d6d6ee/32.png) [@nils](https://discourse.grlib.community/u/nils)\
**Post date:** [10 February 2021 20:52 UTC](https://discourse.grlib.community/t/error-compiling-noel-v-with-modelsim/91/10 "2021-02-10T20:52:22Z")

</div>

Hi Michele,

We will try to update the NOEL-V template designs to make them easier to simulate for the next GRLIB release. In the mean time, I have prepared a simple generic NOEL-V template design which should be easy to simulate in GRLIB. Please download the noelv-generic ([http://gaisler.com/tmp/noelv-generic.tar.gz](http://gaisler.com/tmp/noelv-generic.tar.gz)) template design and place it in the GRLIB/designs directory.

I hope this can get you started trying out our NOEL-V processor.

Regards,  
Nils

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<div class="post-metadata">

**Author:** ![Michele](https://avatars.discourse-cdn.com/v4/letter/m/ed8c4c/32.png) [@Michele](https://discourse.grlib.community/u/Michele)\
**Post date:** [11 February 2021 07:07 UTC](https://discourse.grlib.community/t/error-compiling-noel-v-with-modelsim/91/11 "2021-02-11T07:07:48Z")

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Thank you very much, it works perfectly!

Best regards,

Micheme