# Error compiling Leon3 with Questa for Ultrascale+

**URL:** <https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156>\
**Category:** LEON\
**Created:** [24 June 2021 18:41 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156 "2021-06-24T18:41:29Z")\
**Posts on this page:** 20\
**Page:** 1

<div class="post-metadata">

**Author:** ![mnorris](https://avatars.discourse-cdn.com/v4/letter/m/96bed5/32.png) [@mnorris](https://discourse.grlib.community/u/mnorris)\
**Post date:** [24 June 2021 18:41 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156/1 "2021-06-24T18:41:29Z")

</div>

Hello,

I am a new user to GRLIB. I am trying to generate a Leon3 core for the ZCU102 (Zynq Ultrascale+ MPSoC).There are no example designs for this board, so I am trying to use the ‘leon3mp’ example as my starting point, and will map the technology to inferred.

I am using GRLIB version grlib-gpl-2021.1-b4265.  
I am running bash shell on RH release 7.9.  
I am using the following tools:

```
 Vivado 2020.1
 Questa 2019.4_1  

```

Following the instructions in ‘grlib.pdf’, Section 2.5, I set the following:

export GRLIB=“/mypath/gaisler\_grlib/grlib-gpl-2021.1-b4265”  
export XILINX=“/mypath/tools/xilinx/2020.1/Vivado/2020.1/data”

Then do the following (NOTE: I must specify Questa or I get an error):  
cd grlib-gpl-2021.1-b4265  
make map\_xilinx\_7series\_lib GRLIB\_SIMULATOR=“Questa”  
cd designs/leon3mp  
make sim GRLIB\_SIMULATOR=“Questa”

I get the following errors:

> \*\* Error: (vcom-11) Could not find unisim.vcomponents.
> 
> ###### …/…/lib/techmap/unisim/memory\_ultrascale.vhd(33): use UNISIM.vcomponents.all;
> 
> \*\* Error (suppressible): …/…/lib/techmap/unisim/memory\_ultrascale.vhd(33): (vcom-1195) Cannot find expanded name “unisim.vcomponents”.  
> \*\* Error: …/…/lib/techmap/unisim/memory\_ultrascale.vhd(33): Unknown expanded name.
> 
> ###### …/…/lib/techmap/unisim/memory\_ultrascale.vhd(38): entity ultrascale\_syncram is
> 
> \*\* Note: …/…/lib/techmap/unisim/memory\_ultrascale.vhd(38): VHDL Compiler exiting  
> make[2]: \*\*\* [vsim] Error 2

I next try the following:

cd grlib-gpl-2021.1-b4265  
make clean  
make install-unisim  
make map\_xilinx\_7series\_lib GRLIB\_SIMULATOR=“Questa”  
cd designs/leon3mp  
make clean  
make sim GRLIB\_SIMULATOR=“Questa”

I get the following errors:

> - Error: (vcom-11) Could not find unisim.ramb16\_s36\_s36.
> 
> ###### …/…/lib/techmap/unisim/memory\_unisim.vhd(36): use unisim.RAMB16\_S36\_S36;
> 
> \*\* Error (suppressible): …/…/lib/techmap/unisim/memory\_unisim.vhd(36): (vcom-1195) Cannot find expanded name “unisim.RAMB16\_S36\_S36”.  
> \*\* Error: (vcom-11) Could not find unisim.ramb16\_s36.
> 
> ###### …/…/lib/techmap/unisim/memory\_unisim.vhd(37): use unisim.RAMB16\_S36;
> 
> \*\* Error (suppressible): …/…/lib/techmap/unisim/memory\_unisim.vhd(37): (vcom-1195) Cannot find expanded name “unisim.RAMB16\_S36”.  
> \*\* Error: (vcom-11) Could not find unisim.ramb16\_s18.  
> etc…

I also tried other options, such as:

cd grlib-gpl-2021.1-b4265  
make clean  
make install-unisim  
make map\_xilinx\_7series\_lib GRLIB\_SIMULATOR=“Questa”  
cd designs/leon3mp  
make clean  
make sim GRLIB\_SIMULATOR=“Questa” SKIP\_SIM\_TECHLIBS=“1”

I get the following errors:

> ###### …/…/lib/techmap/unisim/memory\_ultrascale.vhd(32): library unisim;
> 
> \*\* Error: …/…/lib/techmap/unisim/memory\_ultrascale.vhd(32): (vcom-1598) Library “unisim” not found.
> 
> ###### …/…/lib/techmap/unisim/memory\_ultrascale.vhd(33): use UNISIM.vcomponents.all;
> 
> \*\* Error: …/…/lib/techmap/unisim/memory\_ultrascale.vhd(33): (vcom-1136) Unknown identifier “UNISIM”.
> 
> ###### …/…/lib/techmap/unisim/memory\_ultrascale.vhd(38): entity ultrascale\_syncram is
> 
> \*\* Note: …/…/lib/techmap/unisim/memory\_ultrascale.vhd(38): VHDL Compiler exiting

Finally if I do this:

```
cd grlib-gpl-2021.1-b4265 
make clean
make map_xilinx_7series_lib GRLIB_SIMULATOR="Questa" 
cd designs/leon3mp
make clean
make sim GRLIB_SIMULATOR="Questa" TECHLIBS="inferred" 
make sim-launch

```

The compile works successfully, and I am able to run the default simulation.  
However, I’m concerned about this workaround. Is specifying TECHLIBS=inferred okay,  
or am I setting myself up for later problems? Why was this necessary?

For example, I was able to run Vivado P&R (after fixing the targeted device type):  
make vivado-launch

However I found that if I changed the JTAG Debug Link setting to yes (in xconfig),  
I get this error in Vivado:

> [DRC INBB-3] Black Box Instances: Cell ‘ahbjtaggen0.ahbjtag0/tap0/inf.u0’ of type ‘tap\_gen’ has undefined contents and is considered a black box.  
> The contents of this cell must be defined for opt\_design to complete successfully.

I found the component for ‘tap\_gen’ here:  
grlib-gpl-2021.1-b4265/lib/techmap/alltech/alltap.vhd

But I cannot find the entity/architecture for ‘tap\_gen’ in the GRLIB.

I don’t think this problem is related to me using TECHLIBS=inferred, but this is my concern, that I do not have my libraries compiled properly. Is the ‘tap\_gen’ issue a completely separate problem?

This appears similar to another topic (Error compiling NOEL-V with Modelsim), and the resolution sounded like it required a patch to the GRLIB to fix it. Perhaps that is the same for this issue?

Thanks for any support on this.

---

<div class="post-metadata">

**Author:** ![ronnback](https://avatars.discourse-cdn.com/v4/letter/r/f17d59/32.png) [@ronnback](https://discourse.grlib.community/u/ronnback)\
**Post date:** [29 June 2021 11:37 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156/2 "2021-06-29T11:37:05Z")

</div>

Hi,

It should be sufficient to run make map\_xilinx\_7series\_lib for Ultrascale+ devices. make install-unisim is intended for devices using ISE and will copy the simulation models from the Xilinx tool.

Make sure your version of Questasim and Vivado are compatible. If the Questasim version isn’t supported by the Vivado version, the simulation libraries aren’t compiled. The GRLIB script enviroment will automatically add the -quiet flag to the compilation, thereby suppressing any errors from Vivado during the compilation of the simulation libraries.

Best regards,  
Martin

---

<div class="post-metadata">

**Author:** ![mnorris](https://avatars.discourse-cdn.com/v4/letter/m/96bed5/32.png) [@mnorris](https://discourse.grlib.community/u/mnorris)\
**Post date:** [30 June 2021 12:11 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156/3 "2021-06-30T12:11:44Z")

</div>

Martin (@ronnback ),

Thanks for the reply. I am using the following versions:  
Vivado 2020.1  
Questa 2019.4\_1

According to the release notes (ug973) for Vivado 2020.1, the compatible version is 2019.4. We don’t have that exact version installed, but I assumed the 2019.4\_1 would also be compatible.

I will not run the ‘make install-unisim’.

When I run this:  
make map\_xilinx\_7series\_lib GRLIB\_SIMULATOR=“Questa”

I don’t see any errors, and I don’t see errors in the ‘compile\_simlib.log’.

Output when running that command:

> GRLIB settings:  
> GRLIB = /mtcnas/project/janus/mnorris/gaisler\_grlib/grlib-gpl-2021.1-b4265  
> GRLIB\_CONFIG is library default  
> GRLIB\_SIMULATOR = Questa  
> TECHLIBS setting = apa proasic3 axcelerator ec fusion unisim virtex virtex5 secureip unimacro \> altera altera\_mf stratixii eclipsee cycloneiii stratixiii synplify simprim stratixiv proasic3e proasic3l smartfusion2 rtg4 polarfire nx ihp25 sgb25vrh ut025crh virage rh\_lib18t rh\_lib18t\_io2 rh\_lib13t atc18 artisan umc18 virage90 tsmc90 dare nextreme atc18rha\_cell smic13 tm65gplus st65lp st65gp cmos9sf nextreme2 gf65g saed32 gf22fdx  
> Top-level design =  
> Simulation top-level =  
> Scanning libraries:  
> grlib: stdlib util sparc riscv modgen amba dftlib generic\_bm  
> ec: orca  
> unisim: ise  
> secureip: ise  
> unimacro: ise  
> altera: simprims  
> altera\_mf: simprims  
> stratixii: simprims  
> eclipsee: simprims  
> cycloneiii: simprims  
> stratixiii: simprims  
> simprim: vcomponents  
> virage: vcomponents simprims  
> atc18: components  
> umc18: components  
> saed32: components  
> techmap: gencomp alltech inferred ec unisim virtex virtex5 altera\_mf stratixii eclipsee cycloneiii \> stratixiii stratixiv virage atc18 umc18 saed32 maps  
> spw: comp wrapper  
> eth: comp core wrapper  
> opencores: can i2c ge\_1000baseX  
> gaisler: arith memctrl srmmu leon3 leon3v3 leon4 irqmp l2cache/pkg can axi misc ambatest net pci \> uart sim jtag greth spacewire spacefibre usb ddr gr1553b i2c spi grdmac grdmac2 subsys noelv plic \> noelv/subsys leon5 leon5v0  
> esa: memoryctrl pci  
> fmf: utilities flash fifo  
> spansion: flash  
> gsi: ssram  
> micron: sdram  
> cypress: ssram  
> work: debug
> 
> \*\*\*\*\*\* Vivado v2020.1 (64-bit)  
> \*\*\*\* SW Build 2902540 on Wed May 27 19:54:35 MDT 2020  
> \*\*\*\* IP Build 2902112 on Wed May 27 22:43:36 MDT 2020  
> \*\* Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
> 
> INFO: [Common 17-1239] XILINX\_LOCAL\_USER\_DATA is set to ‘0’.  
> source ./xilinx\_lib/\_simlib.tcl  
> compile\_simlib -quiet -directory ./xilinx\_lib/ -family all -language all -simulator questa → no\_ip\_compile -library unisim -library simprim  
> INFO: [Common 17-206] Exiting Vivado at Tue Jun 29 10:49:18 2021…  
> QuestaSim-64 vmap 2019.4\_1 Lib Mapping Utility 2019.11 Nov 12 2019  
> vmap secureip\_ver ./xilinx\_lib/secureip  
> Modifying modelsim.ini  
> QuestaSim-64 vmap 2019.4\_1 Lib Mapping Utility 2019.11 Nov 12 2019  
> vmap secureip ./xilinx\_lib/secureip  
> Modifying modelsim.ini  
> QuestaSim-64 vmap 2019.4\_1 Lib Mapping Utility 2019.11 Nov 12 2019  
> vmap axi\_bfm ./xilinx\_lib/secureip  
> Modifying modelsim.ini  
> QuestaSim-64 vmap 2019.4\_1 Lib Mapping Utility 2019.11 Nov 12 2019  
> vmap unisims\_ver ./xilinx\_lib/unisims\_ver  
> Modifying modelsim.ini  
> QuestaSim-64 vmap 2019.4\_1 Lib Mapping Utility 2019.11 Nov 12 2019  
> vmap unisim ./xilinx\_lib/unisim  
> Modifying modelsim.ini  
> QuestaSim-64 vmap 2019.4\_1 Lib Mapping Utility 2019.11 Nov 12 2019  
> vmap unimacro\_ver ./xilinx\_lib/unimacro\_ver  
> Modifying modelsim.ini  
> QuestaSim-64 vmap 2019.4\_1 Lib Mapping Utility 2019.11 Nov 12 2019  
> vmap unimacro ./xilinx\_lib/unimacro  
> Modifying modelsim.ini  
> QuestaSim-64 vmap 2019.4\_1 Lib Mapping Utility 2019.11 Nov 12 2019  
> vmap simprim\_ver ./xilinx\_lib/simprims\_ver  
> Modifying modelsim.ini  
> QuestaSim-64 vmap 2019.4\_1 Lib Mapping Utility 2019.11 Nov 12 2019  
> vmap unifast\_ver ./xilinx\_lib/unifast\_ver  
> Modifying modelsim.ini  
> QuestaSim-64 vmap 2019.4\_1 Lib Mapping Utility 2019.11 Nov 12 2019  
> vmap unifast ./xilinx\_lib/unifast\_ver  
> Modifying modelsim.ini

Then when I do:  
cd designs/leon3mp  
make sim GRLIB\_SIMULATOR=“Questa”

I get:

> \*\* Error: (vcom-11) Could not find unisim.vcomponents.  
> …/…/lib/techmap/unisim/memory\_ultrascale.vhd(33): use UNISIM.vcomponents.all;  
> \*\* Error (suppressible): …/…/lib/techmap/unisim/memory\_ultrascale.vhd(33): (vcom-1195)  
> Cannot find expanded name “unisim.vcomponents”.  
> \*\* Error: …/…/lib/techmap/unisim/memory\_ultrascale.vhd(33): Unknown expanded name.  
> …/…/lib/techmap/unisim/memory\_ultrascale.vhd(38): entity ultrascale\_syncram is  
> \*\* Note: …/…/lib/techmap/unisim/memory\_ultrascale.vhd(38): VHDL Compiler exiting

Thanks for any help,  
Mike

---

<div class="post-metadata">

**Author:** ![ronnback](https://avatars.discourse-cdn.com/v4/letter/r/f17d59/32.png) [@ronnback](https://discourse.grlib.community/u/ronnback)\
**Post date:** [5 July 2021 11:47 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156/4 "2021-07-05T11:47:22Z")

</div>

Hi Mike,

Can you try compiling the simulation libraries without the -quiet flag, which is added by the GRLIB script environment? It could be that something is happening during compilation. Unfortunately I don’t have access to Questa 2019.4\_1, so I haven’t been able to check this myself.

Best regards,  
Martin

---

<div class="post-metadata">

**Author:** ![mnorris](https://avatars.discourse-cdn.com/v4/letter/m/96bed5/32.png) [@mnorris](https://discourse.grlib.community/u/mnorris)\
**Post date:** [6 July 2021 17:47 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156/5 "2021-07-06T17:47:17Z")

</div>

Martin (@ronnback ),

I removed the -quiet flag from the compile. See the output below. I don’t see any errors. Apologies for the long post, it doesn’t appear I can attach anything but images.

Also, see my earlier error when trying to use the JTAG tap controller:

> [DRC INBB-3] Black Box Instances: Cell ‘ahbjtaggen0.ahbjtag0/tap0/inf.u0’ of type \>‘tap\_gen’ has undefined contents and is considered a black box.  
> The contents of this cell must be defined for opt\_design to complete successfully.

Is it possible the ‘tap\_gen’ entity/architecture are missing from the GRLIB delivery? We are interested in using the JTAG debug option for the Leon3.

Thanks,  
Mike

> GRLIB settings:  
> GRLIB = /mtcnas/project/janus/mnorris/gaisler\_grlib/grlib-gpl-2021.1-b4265  
> GRLIB\_CONFIG is library default  
> GRLIB\_SIMULATOR = Questa  
> TECHLIBS setting = apa proasic3 axcelerator ec fusion unisim virtex virtex5 secureip unimacro altera altera\_mf stratixii eclipsee cycloneiii stratixiii synplify simprim stratixiv proasic3e proasic3l smartfusion2 rtg4 polarfire nx ihp25 sgb25vrh ut025crh virage rh\_lib18t rh\_lib18t\_io2 rh\_lib13t atc18 artisan umc18 virage90 tsmc90 dare nextreme atc18rha\_cell smic13 tm65gplus st65lp st65gp cmos9sf nextreme2 gf65g saed32 gf22fdx  
> Top-level design =  
> Simulation top-level =  
> Scanning libraries:  
> grlib: stdlib util sparc riscv modgen amba dftlib generic\_bm  
> ec: orca  
> unisim: ise  
> secureip: ise  
> unimacro: ise  
> altera: simprims  
> altera\_mf: simprims  
> stratixii: simprims  
> eclipsee: simprims  
> cycloneiii: simprims  
> stratixiii: simprims  
> simprim: vcomponents  
> virage: vcomponents simprims  
> atc18: components  
> umc18: components  
> saed32: components  
> techmap: gencomp alltech inferred ec unisim virtex virtex5 altera\_mf stratixii eclipsee cycloneiii stratixiii stratixiv virage atc18 umc18 saed32 maps  
> spw: comp wrapper  
> eth: comp core wrapper  
> opencores: can i2c ge\_1000baseX  
> gaisler: arith memctrl srmmu leon3 leon3v3 leon4 irqmp l2cache/pkg can axi misc ambatest net pci uart sim jtag greth spacewire spacefibre usb ddr gr1553b i2c spi grdmac grdmac2 subsys noelv plic noelv/subsys leon5 leon5v0  
> esa: memoryctrl pci  
> fmf: utilities flash fifo  
> spansion: flash  
> gsi: ssram  
> micron: sdram  
> cypress: ssram  
> work: debug
> 
> \*\*\*\*\*\* Vivado v2020.1 (64-bit)  
> \*\*\*\* SW Build 2902540 on Wed May 27 19:54:35 MDT 2020  
> \*\*\*\* IP Build 2902112 on Wed May 27 22:43:36 MDT 2020  
> \*\* Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
> 
> INFO: [Common 17-1239] XILINX\_LOCAL\_USER\_DATA is set to ‘0’.  
> source ./xilinx\_lib/\_simlib.tcl
> 
> # compile\_simlib -directory ./xilinx\_lib/ -family all -language all -simulator questa -no\_ip\_compile -library unisim -library simprim
> 
> INFO: [Vivado 12-5496] Finding simulator executables and checking version…  
> WARNING: [Vivado 12-5495] Detected incompatible questasim simulator installation version ‘2019’! The supported simulator version for the current Vivado release is ‘2019.4’.  
> INFO: [Vivado 12-5498] Processing source library information for the selected device family (default:all) …
> 
> Compiling libraries for ‘questasim’ simulator in ‘/mtcnas/project/janus/mnorris/gaisler\_grlib/grlib-gpl-2021.1-b4265/xilinx\_lib’  
> → Compiling ‘verilog.secureip’ library…  
> \> Source Library = ‘/mtcnas/tools/xilinx/2020.1/Vivado/2020.1/data/secureip’  
> \> Compiled Path = ‘/mtcnas/project/janus/mnorris/gaisler\_grlib/grlib-gpl-2021.1-b4265/xilinx\_lib/secureip’  
> \> Log File = ‘/mtcnas/project/janus/mnorris/gaisler\_grlib/grlib-gpl-2021.1-b4265/xilinx\_lib/secureip/.cxl.verilog.secureip.secureip.lin64.log’
> 
> compile\_simlib[verilog.secureip]: 0 error(s), 10 warning(s), 20.00 % complete  
> → Compiling ‘vhdl.unisim’ library…  
> \> Source Library = ‘/mtcnas/tools/xilinx/2020.1/Vivado/2020.1/data/vhdl/src/unisims’  
> \> Compiled Path = ‘/mtcnas/project/janus/mnorris/gaisler\_grlib/grlib-gpl-2021.1-b4265/xilinx\_lib/unisim’  
> \> Log File = ‘/mtcnas/project/janus/mnorris/gaisler\_grlib/grlib-gpl-2021.1-b4265/xilinx\_lib/unisim/.cxl.vhdl.unisim.unisim.lin64.log’  
> → Compiling ‘vhdl.unisim:vhdl.unimacro’ library…  
> \> Source Library = ‘/mtcnas/tools/xilinx/2020.1/Vivado/2020.1/data/vhdl/src/unimacro’  
> \> Compiled Path = ‘/mtcnas/project/janus/mnorris/gaisler\_grlib/grlib-gpl-2021.1-b4265/xilinx\_lib/unimacro’  
> \> Log File = ‘/mtcnas/project/janus/mnorris/gaisler\_grlib/grlib-gpl-2021.1-b4265/xilinx\_lib/unimacro/.cxl.vhdl.unimacro.unimacro.lin64.log’  
> compile\_simlib[vhdl.unisim:vhdl.unimacro]: 0 error(s), 0 warning(s)  
> → Compiling ‘vhdl.unisim:vhdl.unifast’ library…  
> \> Source Library = ‘/mtcnas/tools/xilinx/2020.1/Vivado/2020.1/data/vhdl/src/unifast’  
> \> Compiled Path = ‘/mtcnas/project/janus/mnorris/gaisler\_grlib/grlib-gpl-2021.1-b4265/xilinx\_lib/unifast’  
> \> Log File = ‘/mtcnas/project/janus/mnorris/gaisler\_grlib/grlib-gpl-2021.1-b4265/xilinx\_lib/unifast/.cxl.vhdl.unifast.unifast.lin64.log’  
> compile\_simlib[vhdl.unisim:vhdl.unifast]: 0 error(s), 0 warning(s)
> 
> compile\_simlib[vhdl.unisim]: 0 error(s), 0 warning(s), 60.00 % complete  
> → Compiling ‘verilog.unisim’ library…  
> \> Source Library = ‘/mtcnas/tools/xilinx/2020.1/Vivado/2020.1/data/verilog/src’  
> \> Compiled Path = ‘/mtcnas/project/janus/mnorris/gaisler\_grlib/grlib-gpl-2021.1-b4265/xilinx\_lib/unisims\_ver’  
> \> Log File = ‘/mtcnas/project/janus/mnorris/gaisler\_grlib/grlib-gpl-2021.1-b4265/xilinx\_lib/unisims\_ver/.cxl.verilog.unisim.unisims\_ver.lin64.log’  
> → Compiling ‘verilog.unisim:verilog.unimacro’ library…  
> \> Source Library = ‘/mtcnas/tools/xilinx/2020.1/Vivado/2020.1/data/verilog/src/unimacro’  
> \> Compiled Path = ‘/mtcnas/project/janus/mnorris/gaisler\_grlib/grlib-gpl-2021.1-b4265/xilinx\_lib/unimacro\_ver’  
> \> Log File = ‘/mtcnas/project/janus/mnorris/gaisler\_grlib/grlib-gpl-2021.1-b4265/xilinx\_lib/unimacro\_ver/.cxl.verilog.unimacro.unimacro\_ver.lin64.log’  
> compile\_simlib[verilog.unisim:verilog.unimacro]: 0 error(s), 0 warning(s)  
> → Compiling ‘verilog.unisim:verilog.unifast’ library…  
> \> Source Library = ‘/mtcnas/tools/xilinx/2020.1/Vivado/2020.1/data/verilog/src/unifast’  
> \> Compiled Path = ‘/mtcnas/project/janus/mnorris/gaisler\_grlib/grlib-gpl-2021.1-b4265/xilinx\_lib/unifast\_ver’  
> \> Log File = ‘/mtcnas/project/janus/mnorris/gaisler\_grlib/grlib-gpl-2021.1-b4265/xilinx\_lib/unifast\_ver/.cxl.verilog.unifast.unifast\_ver.lin64.log’  
> compile\_simlib[verilog.unisim:verilog.unifast]: 0 error(s), 0 warning(s)
> 
> compile\_simlib[verilog.unisim]: 0 error(s), 0 warning(s), 80.00 % complete  
> → Compiling ‘verilog.simprim’ library…  
> \> Source Library = ‘/mtcnas/tools/xilinx/2020.1/Vivado/2020.1/data/verilog/src/unisims’  
> \> Compiled Path = ‘/mtcnas/project/janus/mnorris/gaisler\_grlib/grlib-gpl-2021.1-b4265/xilinx\_lib/simprims\_ver’  
> \> Log File = ‘/mtcnas/project/janus/mnorris/gaisler\_grlib/grlib-gpl-2021.1-b4265/xilinx\_lib/simprims\_ver/.cxl.verilog.simprim.simprims\_ver.lin64.log’
> 
> compile\_simlib[verilog.simprim]: 0 error(s), 0 warning(s), 100.00 % complete  
> Copying setup file ‘modelsim.ini’ to ‘/mtcnas/project/janus/mnorris/gaisler\_grlib/grlib-gpl-2021.1-b4265/./xilinx\_lib//modelsim.ini’ …
> 
> * * *
> 
> - 
> 
> ```
> COMPILATION SUMMARY *
> 
> ```
> 
> - 
> 
> ```
> *
> 
> ```
> 
> - Simulator used: questasim \*
> - Compiled on: Tue Jul 6 09:54:17 2021 \*
> - 
> 
> ```
> *
> 
> ```
> 
> * * *
> 
> - Library | Language | Mapped Library Name | Error(s) | Warning(s) \*  
> _---------------------------------------------------------------------------------------------------------------------_
> - secureip | verilog | secureip | 0 | 10 \*
> 
> * * *
> 
> - unisim | vhdl | unisim | 0 | 0 \*
> 
> * * *
> 
> - unimacro | vhdl | unimacro | 0 | 0 \*
> 
> * * *
> 
> - unifast | vhdl | unifast | 0 | 0 \*
> 
> * * *
> 
> - unisim | verilog | unisims\_ver | 0 | 0 \*
> 
> * * *
> 
> - unimacro | verilog | unimacro\_ver | 0 | 0 \*
> 
> * * *
> 
> - unifast | verilog | unifast\_ver | 0 | 0 \*
> 
> * * *
> 
> - simprim | verilog | simprims\_ver | 0 | 0 \*
> 
> * * *
> 
> INFO: [Vivado 12-7167] Writing compiled library information…  
> INFO: [Vivado 12-7165] Finished writing compiled library information.  
> compile\_simlib: Time (s): cpu = 00:31:59 ; elapsed = 00:33:47 . Memory (MB): peak = 2209.219 ; gain = 0.004 ; free physical = 6044 ; free virtual = 85804  
> INFO: [Common 17-206] Exiting Vivado at Tue Jul 6 10:28:03 2021…  
> QuestaSim-64 vmap 2019.4\_1 Lib Mapping Utility 2019.11 Nov 12 2019  
> vmap secureip\_ver ./xilinx\_lib/secureip  
> Modifying modelsim.ini  
> QuestaSim-64 vmap 2019.4\_1 Lib Mapping Utility 2019.11 Nov 12 2019  
> vmap secureip ./xilinx\_lib/secureip  
> Modifying modelsim.ini  
> QuestaSim-64 vmap 2019.4\_1 Lib Mapping Utility 2019.11 Nov 12 2019  
> vmap axi\_bfm ./xilinx\_lib/secureip  
> Modifying modelsim.ini  
> QuestaSim-64 vmap 2019.4\_1 Lib Mapping Utility 2019.11 Nov 12 2019  
> vmap unisims\_ver ./xilinx\_lib/unisims\_ver  
> Modifying modelsim.ini  
> QuestaSim-64 vmap 2019.4\_1 Lib Mapping Utility 2019.11 Nov 12 2019  
> vmap unisim ./xilinx\_lib/unisim  
> Modifying modelsim.ini  
> QuestaSim-64 vmap 2019.4\_1 Lib Mapping Utility 2019.11 Nov 12 2019  
> vmap unimacro\_ver ./xilinx\_lib/unimacro\_ver  
> Modifying modelsim.ini  
> QuestaSim-64 vmap 2019.4\_1 Lib Mapping Utility 2019.11 Nov 12 2019  
> vmap unimacro ./xilinx\_lib/unimacro  
> Modifying modelsim.ini  
> QuestaSim-64 vmap 2019.4\_1 Lib Mapping Utility 2019.11 Nov 12 2019  
> vmap simprim\_ver ./xilinx\_lib/simprims\_ver  
> Modifying modelsim.ini  
> QuestaSim-64 vmap 2019.4\_1 Lib Mapping Utility 2019.11 Nov 12 2019  
> vmap unifast\_ver ./xilinx\_lib/unifast\_ver  
> Modifying modelsim.ini  
> QuestaSim-64 vmap 2019.4\_1 Lib Mapping Utility 2019.11 Nov 12 2019  
> vmap unifast ./xilinx\_lib/unifast\_ver  
> Modifying modelsim.ini

-Mike

---

<div class="post-metadata">

**Author:** ![ronnback](https://avatars.discourse-cdn.com/v4/letter/r/f17d59/32.png) [@ronnback](https://discourse.grlib.community/u/ronnback)\
**Post date:** [7 July 2021 13:39 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156/6 "2021-07-07T13:39:21Z")

</div>

Hi Mike,

The inferred TAP is not included in the GPL package.

It is strange the simulator can not find unisim.vcomponents, since it seems to be compiled. I haven’t been able to reproduce this.

Under xilinx\_lib/unisim/ there should be a file called .cxl.vhdl.unisim.unisim.lin64.cmf, listing which files under unisim that are compiled.

Best regards,

Martin

---

<div class="post-metadata">

**Author:** ![mnorris](https://avatars.discourse-cdn.com/v4/letter/m/96bed5/32.png) [@mnorris](https://discourse.grlib.community/u/mnorris)\
**Post date:** [7 July 2021 15:58 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156/7 "2021-07-07T15:58:44Z")

</div>

Martin (@ronnback ),

I see that .cxl file. The only line that has anything including “vcomp” is:

/mtcnas/tools/xilinx/2020.1/Vivado/2020.1/data/vhdl/src/unisims/unisim\_retarget\_VCOMP.vhdp

So you are saying that if we are intending to target the “inferred” technology, then we cannot use the JTAG debug option? Has that always been the case? I am discussing my experience with another group, and they had used an older GRLIB (2017.2), and I believe they also targeted “inferred” technology, and had enabled the JTAG debug option.

Thanks,  
Mike

---

<div class="post-metadata">

**Author:** ![ronnback](https://avatars.discourse-cdn.com/v4/letter/r/f17d59/32.png) [@ronnback](https://discourse.grlib.community/u/ronnback)\
**Post date:** [7 July 2021 16:15 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156/8 "2021-07-07T16:15:37Z")

</div>

Hi Mike,

tap\_inferred.vhd has not been in the GPL package previously, only in commercial packages.

Best regards,  
Martin

---

<div class="post-metadata">

**Author:** ![mnorris](https://avatars.discourse-cdn.com/v4/letter/m/96bed5/32.png) [@mnorris](https://discourse.grlib.community/u/mnorris)\
**Post date:** [7 July 2021 18:10 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156/9 "2021-07-07T18:10:41Z")

</div>

Martin,

Okay thanks for the clarification. Any insight into the problem with my compilation?  
I still get this:

> \*\* Error: (vcom-11) Could not find unisim.vcomponents.  
> …/…/lib/techmap/unisim/memory\_ultrascale.vhd(33): use \>UNISIM.vcomponents.all;  
> \*\* Error (suppressible): …/…/lib/techmap/unisim/memory\_ultrascale.vhd(33): (vcom-\>1195) Cannot find expanded name “unisim.vcomponents”.  
> \*\* Error: …/…/lib/techmap/unisim/memory\_ultrascale.vhd(33): Unknown expanded name.  
> …/…/lib/techmap/unisim/memory\_ultrascale.vhd(38): entity ultrascale\_syncram is  
> \*\* Note: …/…/lib/techmap/unisim/memory\_ultrascale.vhd(38): VHDL Compiler exiting

Thanks,  
Mike

---

<div class="post-metadata">

**Author:** ![ronnback](https://avatars.discourse-cdn.com/v4/letter/r/f17d59/32.png) [@ronnback](https://discourse.grlib.community/u/ronnback)\
**Post date:** [8 July 2021 08:50 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156/10 "2021-07-08T08:50:43Z")

</div>

No, unfortunately not. I haven’t been able to reproduce it with the versions of the tools I have access to. This error suggests that vcomponents haven’t been properly compiled or mapped.

Best regards,  
Martin

---

<div class="post-metadata">

**Author:** ![mnorris](https://avatars.discourse-cdn.com/v4/letter/m/96bed5/32.png) [@mnorris](https://discourse.grlib.community/u/mnorris)\
**Post date:** [16 July 2021 18:30 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156/11 "2021-07-16T18:30:52Z")

</div>

Martin (@ronnback ),

Thanks for your help looking into this. I’m a bit confused about the JTAG debug option. As I mentioned, we are targeting the Zynq Ultrascale+ MPSoC. Since there are no design examples for this board, I had to select “inferred” for the technology. Are you saying there is no TAP controller included for the “inferred” option? How do users use the JTAG debug option, when they are targeting designs that are not included in the examples?

Thanks,  
Mike

---

<div class="post-metadata">

**Author:** ![mnorris](https://avatars.discourse-cdn.com/v4/letter/m/96bed5/32.png) [@mnorris](https://discourse.grlib.community/u/mnorris)\
**Post date:** [3 August 2021 16:45 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156/12 "2021-08-03T16:45:02Z")

</div>

Martin (@ronnback ),

FYI, I also get the same compilation error (regarding unisim.vcomponents), using:

Release: grlib-gpl-2021.2-b4267  
Xilinx : 2021.1  
Questa : 2020.4\_2

-Mike

---

<div class="post-metadata">

**Author:** ![ronnback](https://avatars.discourse-cdn.com/v4/letter/r/f17d59/32.png) [@ronnback](https://discourse.grlib.community/u/ronnback)\
**Post date:** [23 August 2021 14:07 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156/13 "2021-08-23T14:07:39Z")

</div>

Hi Mike,

Sorry for the lack of a response on my side. I have been out of office.

Have you made sure the tool versions are compatible. If the QuestaSim version is not supported by the version of Vivado you are using, you might encounter issues with compiling the Xilinx libraries. If you look at the combination of Vivado and QuestaSim versions, Vivado warns that the supported version of QuestaSim is 2019.4, so somehow your QuestaSim version identifies itself as “2019”:

“INFO: [Vivado 12-5496] Finding simulator executables and checking version…  
WARNING: [Vivado 12-5495] Detected incompatible questasim simulator installation version ‘2019’! The supported simulator version for the current Vivado release is ‘2019.4’.”

Could you try running the compilation of the Xilinx libraries without the quiet flag for the new combination to ensure that Vivado doesn’t complain about the QuestaSim version.

Best regards,  
Martin

---

<div class="post-metadata">

**Author:** ![mnorris](https://avatars.discourse-cdn.com/v4/letter/m/96bed5/32.png) [@mnorris](https://discourse.grlib.community/u/mnorris)\
**Post date:** [24 August 2021 14:13 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156/14 "2021-08-24T14:13:40Z")

</div>

Martin (@ronnback),

We installed the proper version of Questa supported by the version of Vivado (according to the Vivado release notes). I do not get a warning about incompatible versions, but I’m still having issues. So my setup is now:

Release: grlib-gpl-2021.2-b4267  
Xilinx : 2021.1  
Questa : 2020.4

I just want to clarify something. In the ‘GRLIB IP Library User’s Manual’, section 2.5, there are two statements:

_The commands described below can be performed from the root of the GRLIB tree if the variable $GRLIB has been set to point to the GRLIB base._

_The commands can also be executed from within any template design directory under designs/._

I have the **GRLIB** variable set properly. So when I run the **make map\_xilinx\_7series\_lib GRLIB\_SIMULATOR=“Questa”** command, am I supposed to run it from the root of the **grlib-gpl-2021.2-b4267** project, or am I supposed to run it from the **designs/leon3mp** directory, where I want to run my simulation?

Thanks,  
Mike

---

<div class="post-metadata">

**Author:** ![ronnback](https://avatars.discourse-cdn.com/v4/letter/r/f17d59/32.png) [@ronnback](https://discourse.grlib.community/u/ronnback)\
**Post date:** [24 August 2021 14:30 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156/15 "2021-08-24T14:30:30Z")

</div>

Hi Mike

I would recommend running the **make map\_xilinx\_7series\_lib** command from the **designs/leon3mp** directory.

Best regards,

Martin

---

<div class="post-metadata">

**Author:** ![mnorris](https://avatars.discourse-cdn.com/v4/letter/m/96bed5/32.png) [@mnorris](https://discourse.grlib.community/u/mnorris)\
**Post date:** [24 August 2021 16:47 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156/16 "2021-08-24T16:47:24Z")

</div>

Martin (@ronnback ),

Okay, thanks. So I ran the following commands in the **designs/leon3mp** directory:

**make map\_xilinx\_7series\_lib GRLIB\_SIMULATOR=“Questa”**  
**make sim GRLIB\_SIMULATOR=“Questa”**

Now I get several of these errors:

> vcom -93 -work techmap …/…/lib/techmap/virtex/memory\_virtex.vhd  
> \*\* Error: (vcom-11) Could not find unisim.ramb4\_s1.  
> …/…/lib/techmap/virtex/memory\_virtex.vhd(34): use unisim.RAMB4\_S1;  
> \*\* Error (suppressible): …/…/lib/techmap/virtex/memory\_virtex.vhd(34): (vcom-1195) Cannot find expanded name “unisim.RAMB4\_S1”.  
> \*\* Error: (vcom-11) Could not find unisim.ramb4\_s2.  
> …/…/lib/techmap/virtex/memory\_virtex.vhd(35): use unisim.RAMB4\_S2;  
> \*\* Error (suppressible): …/…/lib/techmap/virtex/memory\_virtex.vhd(35): (vcom-1195) Cannot find expanded name “unisim.RAMB4\_S2”.

Any idea why I’m getting these?  
Thanks,  
Mike

---

<div class="post-metadata">

**Author:** ![ronnback](https://avatars.discourse-cdn.com/v4/letter/r/f17d59/32.png) [@ronnback](https://discourse.grlib.community/u/ronnback)\
**Post date:** [24 August 2021 17:01 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156/17 "2021-08-24T17:01:38Z")

</div>

Hi Mike

From your previous screenshot, it looked as if you were including quite a few technologies. Make sure you set TECHLIBS to unisim for Ultrascale+ devices (cf the template designs for the KCU105 board).

Best regards,  
Martin

---

<div class="post-metadata">

**Author:** ![mnorris](https://avatars.discourse-cdn.com/v4/letter/m/96bed5/32.png) [@mnorris](https://discourse.grlib.community/u/mnorris)\
**Post date:** [24 August 2021 17:09 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156/18 "2021-08-24T17:09:32Z")

</div>

Martin,

I’m just trying to get a Questa compile working with the default settings in the **designs/leon3mp** directory. I’m not making any changes to the Makefile settings. The Makefile in that directory has the following:

> GRLIB=…/…  
> TOP=leon3mp  
> BOARD=gr-cpci-xc4v  
> include $(GRLIB)/boards/$(BOARD)/Makefile.inc  
> DEVICE=$(PART)-$(PACKAGE)$(SPEED)  
> UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf  
> QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf  
> EFFORT=std  
> XSTOPT=  
> SYNPOPT=“set\_option -pipe 0; set\_option -retiming 0; set\_option -write\_apr\_constraint 0”  
> VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd  
> VHDLSIMFILES=testbench.vhd  
> SIMTOP=testbench  
> SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc  
> BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut  
> CLEAN=soft-clean
> 
> TECHLIBS = unisim  
> DIRSKIP = leon4v0  
> include $(GRLIB)/bin/Makefile  
> include $(GRLIB)/software/leon3/Makefile

So, basically I’m just trying to get the leon3mp design to compile with Questa, straight out of the box from the GRLIB delivery, and it’s getting that error.

Thanks,  
Mike

---

<div class="post-metadata">

**Author:** ![ronnback](https://avatars.discourse-cdn.com/v4/letter/r/f17d59/32.png) [@ronnback](https://discourse.grlib.community/u/ronnback)\
**Post date:** [25 August 2021 05:28 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156/19 "2021-08-25T05:28:15Z")

</div>

Hi Mike,

Sorry. I focused on the Zynq Ultrascale+ and thought you had already made the necessary changes to port a design to the ultrascale+ technology. The leon3mp template design targets Virtex4, which uses the virtex technology map. In order to build this design out of the box, you need to use ISE. If you simply want to build an unaltered template design with Vivado, any of the 7-series or Ultrascale designs is a better starting point.

Best regars,  
Martin

---

<div class="post-metadata">

**Author:** ![mnorris](https://avatars.discourse-cdn.com/v4/letter/m/96bed5/32.png) [@mnorris](https://discourse.grlib.community/u/mnorris)\
**Post date:** [25 August 2021 17:23 UTC](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156/20 "2021-08-25T17:23:20Z")

</div>

Martin (@ronnback),

Okay, thanks, that makes sense why I’m getting that error.

So next I modified the **./designs/leon3mp/Makefile** as follows:

> GRLIB=…/…  
> TOP=leon3mp  
> BOARD=xilinx\_zcu102  
> include $(GRLIB)/boards/$(BOARD)/Makefile.inc  
> DEVICE=$(PART)-$(PACKAGE)$(SPEED)  
> EFFORT=std  
> XSTOPT=  
> SYNPOPT=“set\_option -pipe 0; set\_option -retiming 0; set\_option -write\_apr\_constraint 0”  
> VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd  
> VHDLSIMFILES=testbench.vhd  
> SIMTOP=testbench  
> CLEAN=soft-clean  
> TECHLIBS = unisim  
> DIRSKIP = leon4v0  
> include $(GRLIB)/bin/Makefile  
> include $(GRLIB)/software/leon3/Makefile

And then created a file **boards/xilinx\_zcu102/Makefile.inc** :

> TECHNOLOGY=ZynqU  
> PART=xczu9eg  
> PACKAGE=ffvb1156  
> SPEED=-2-e

Then ran the following in **designs/leon3mp** :

> make map\_xilinx\_7series\_lib GRLIB\_SIMULATOR=“Questa”  
> make sim GRLIB\_SIMULATOR=“Questa”  
> make sim-launch  
> make vivado-launch

All of these completed without any issue! However, we want to enable JTAG Debugging in our design (which I mentioned earlier in this post). If I open **xconfig** and just enable JTAG Debug, but keep **Target technology=Inferred** , I get the following error in Vivado:

> [DRC INBB-3] Black Box Instances: Cell ‘ahbjtaggen0.ahbjtag0/tap0/inf.u0’ of type ‘tap\_gen’ has undefined contents and is considered a black box. The contents of this cell must be defined for opt\_design to complete successfully.

I believe you mentioned that “inferred” technology does not include support for a TAP controller. So, next I set **Target technology=Xilinx-KintexUltra** , since this is the only Ultrascale option I see.

When I run Vivado, I don’t see any issue with the TAP controller, but now I get this:

> [DRC INBB-3] Black Box Instances: Cell ‘can\_pads.can\_tx\_pad/xcv.x0’ of type ‘unisim\_outpad\_\_parameterized1\_247’ has undefined contents and is considered a black box. The contents of this cell must be defined for opt\_design to complete successfully.

This error has me baffled, because I can see the Xilinx primitive (OBUF) instantiated in the Questa simulation, but for some reason Vivado treats the pad as a black-box. If I comment-out that **can\_tx\_pad** instance in the **leon3mp.vhd** file, that resolves that error, but then I get another error in another pad library.

Is there something wrong with my setup? Is this flow supposed to work for Zynq Ultrascale (ZCU102) I’m targeting?

Thanks,  
Mike

[Next page](https://discourse.grlib.community/t/error-compiling-leon3-with-questa-for-ultrascale/156.md?page=2)