# Debugging NOEL-V Over a JTAG Tunnel with OpenOCD

**URL:** <https://discourse.grlib.community/t/debugging-noel-v-over-a-jtag-tunnel-with-openocd/552>\
**Category:** NOEL-V\
**Created:** [12 January 2026 08:45 UTC](https://discourse.grlib.community/t/debugging-noel-v-over-a-jtag-tunnel-with-openocd/552 "2026-01-12T08:45:08Z")\
**Posts on this page:** 2\
**Page:** 1

<div class="post-metadata">

**Author:** ![WEI](https://avatars.discourse-cdn.com/v4/letter/w/90ced4/32.png) [@WEI](https://discourse.grlib.community/u/WEI)\
**Post date:** [12 January 2026 08:45 UTC](https://discourse.grlib.community/t/debugging-noel-v-over-a-jtag-tunnel-with-openocd/552/1 "2026-01-12T08:45:08Z")

</div>

Hello,

To reuse the same JTAG cable for both FPGA configuration and NOEL debugging, I chose the AHBJTAGRV with Xilinx FPGA TAP as the debugging link.

```vhdl
mon_ocd : ahbjtagrv
generic map (tech => CFG_AHB_JTAG_TEK, dtm_sel => 2,
  hindex_gr => DMIDX_DTM_GR, hindex_rv => DMIDX_DTM_RV,
  nsync => 2, tapopt => 0,
  ainst_gr => 2, dinst_gr => 3, ainst_rv => 16, dinst_rv => 17,
  scantest => 0, oepol => 1, versel => 1)
port map (rstn, mclk, '0', '0', '0', open,
  dbgmi(DMIDX_DTM_GR), dbgmo(DMIDX_DTM_GR), dbgmi(DMIDX_DTM_RV), dbgmo(DMIDX_DTM_RV),
  open, open, open, open, open, open, open, '0', rstn, open, '0', open, open, open);

```

I can debug the design with GRMON, but I failed to debug it on the JTAG tunnel with OpenOCD.

```auto
source [find interface/ftdi/digilent-hs1.cfg]
ftdi tdo_sample_edge falling
transport select jtag
adapter speed 50000

set _CHIPNAME GRLIB
set _CPUNAME NOELV
set _TARGETNAME $_CHIPNAME.$_CPUNAME
jtag newtap $_CHIPNAME $_CPUNAME -irlen 6 -expected-id 0x04A62093
target create $_TARGETNAME.C0 riscv -chain-position $_TARGETNAME

# param 1: width of tunnel instruction register (6 bits)
# param 2: 1 = tunneled data register mode
# 0 = nested TAP mode
riscv use_bscan_tunnel 6 1

# Scan Command Command Code[5:0] Description
# USER1 000010 / 0x02 Access user-defined register 1
# USER2 000011 / 0x03 Access user-defined register 2
# USER3 100010 / 0x22 Access user-defined register 3
# USER4 100011 / 0x23 Access user-defined register 4
riscv set_bscan_tunnel_ir 0x02

init
halt

```

The log is as follows

```auto
Open On-Chip Debugger 0.12.C0 (2025-12-11) [https://github.com/sysprogs/openocd]
Licensed under GNU GPL v2
libusb1 d52e355daa09f17ce64819122cb067b8a2ee0d4b
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
Info : Simple Register based Bscan Tunnel Selected
Info : Bscan tunnel IR 0x2 selected
Info : clock speed 100 kHz
Info : JTAG tap: GRLIB.NOELV tap/device found: 0x04a62093 (mfg: 0x049 (Xilinx), part: 0x4a62, ver: 0x0)
Error: [GRLIB.NOELV.C0] Debug Module did not become active in 5 s. Increase the timeout with 'riscv set_command_timeout_sec'.
Error: [GRLIB.NOELV.C0] Examination failed
Warn : target GRLIB.NOELV.C0 examination failed
Info : [GRLIB.NOELV.C0] starting gdb server on 3333
Info : Listening on port 3333 for gdb connections
Error: Target not examined yet
.\ocd.cfg:16: Error:
Traceback (most recent call last):
  File ".\ocd.cfg", line 16, in script
    halt
Error: [GRLIB.NOELV.C0] Unsupported DTM version: -1
Error: [GRLIB.NOELV.C0] Could not identify target type.

```

The OpenOCD seems to only support one BSCANE2 tunnel, while the AHBJTAGRV has two BSCANE2 for ADATA and DDATA select.

I am not too sure about my analysis, do you have any tips ?

---

<div class="post-metadata">

**Author:** ![WEI](https://avatars.discourse-cdn.com/v4/letter/w/90ced4/32.png) [@WEI](https://discourse.grlib.community/u/WEI)\
**Post date:** [28 January 2026 13:36 UTC](https://discourse.grlib.community/t/debugging-noel-v-over-a-jtag-tunnel-with-openocd/552/2 "2026-01-28T13:36:18Z")

</div>

The problem is solved, thank you for your attention!

The following solution is provided for reference.

```auto
# Xilinx TAP Workround

 # TAP @ Xilinx | RTL @ ahbjtagrv instance
 # Scan Command Command Code[5:0] Description | taptecharg
 # USER1 000010 / 0x02 Access user-defined register 1 | 0
 # USER2 000011 / 0x03 Access user-defined register 2 | 0
 # USER3 100010 / 0x22 Access user-defined register 3 | 1
 # USER4 100011 / 0x23 Access user-defined register 4 | 1

 # DTM @ RISC-V Debug Spec
 # 0x00 BYPASS JTAG recommends this encoding
 # 0x01 IDCODE JTAG recommends this encoding --> 0x09 @ Xilinx TAP
 # 0x10 DTM Control and Status (dtmcs) For Debugging --> 0x02 @ Xilinx TAP
 # 0x11 Debug Module Interface Access (dmi) For Debugging --> 0x03 @ Xilinx TAP

 riscv set_ir idcode 0x09
 riscv set_ir dtmcs 0x02
 riscv set_ir dmi 0x03

```

and the following log is provided for reference.

```auto
Open On-Chip Debugger 0.12.0 (2025-12-11) [https://github.com/sysprogs/openocd]
Licensed under GNU GPL v2
libusb1 d52e355daa09f17ce64819122cb067b8a2ee0d4b
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
Info : clock speed 50000 kHz
Info : JTAG tap: GRLIB.NOELV tap/device found: 0x04a62093 (mfg: 0x049 (Xilinx), part: 0x4a62, ver: 0x0)
Info : [GRLIB.NOELV.0] datacount=4 progbufsize=8
Info : [GRLIB.NOELV.0] Examined RISC-V core
Info : [GRLIB.NOELV.0] XLEN=64, misa=0x80000000009411af
Info : [GRLIB.NOELV.0] Examination succeed
Info : [GRLIB.NOELV.1] datacount=4 progbufsize=8
Info : [GRLIB.NOELV.1] Examined RISC-V core
Info : [GRLIB.NOELV.1] XLEN=64, misa=0x80000000009411af
Info : [GRLIB.NOELV.1] Examination succeed
Info : [GRLIB.NOELV.0] starting gdb server on 3333
Info : Listening on port 3333 for gdb connections
Info : [GRLIB.NOELV.1] starting gdb server on 3334
Info : Listening on port 3334 for gdb connections
GRLIB.NOELV.0 halted due to undefined.
GRLIB.NOELV.1 halted due to undefined.

    TargetName Type Endian TapName State
-- ------------------ ---------- ------ ------------------ ------------
 0 GRLIB.NOELV.0 riscv little GRLIB.NOELV halted
 1* GRLIB.NOELV.1 riscv little GRLIB.NOELV halted
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections

```