# Can RGMII IP be used for Xilinx UltraScale technology?
**URL:** https://discourse.grlib.community/t/can-rgmii-ip-be-used-for-xilinx-ultrascale-technology/464
**Category:** Uncategorized
**Created:** [14 January 2025 08:03 UTC](https://discourse.grlib.community/t/can-rgmii-ip-be-used-for-xilinx-ultrascale-technology/464 "2025-01-14T08:03:57Z")
**Posts on this page:** 5
**Page:** 1
### Author:  [@WEI](https://discourse.grlib.community/u/WEI)
#### Post date: [14 January 2025 08:03 UTC](https://discourse.grlib.community/t/can-rgmii-ip-be-used-for-xilinx-ultrascale-technology/464/1 "2025-01-14T08:03:57Z")
Hi, has anyone used the RGMII IP to adapt GMII/RGMII?
In GRLIB, the ‘RGMII’ uses IDDR and ODDR primitives, but it seems that the ‘unisim\_oddd\_reg’ entity does not have support for Xilinx UltraScale technology.
How should I handle this, or are there any other solutions that support RGMII for GRETH ?
---
### Author:  [@WEI](https://discourse.grlib.community/u/WEI)
#### Post date: [31 January 2025 16:31 UTC](https://discourse.grlib.community/t/can-rgmii-ip-be-used-for-xilinx-ultrascale-technology/464/2 "2025-01-31T16:31:06Z")
I made a small tech patch, now, it is working.
```auto
--- grlib-gpl-2024.4-b4295\lib\techmap\unisim\ddr_unisim.vhd.bak 2024-12-23 20:57:56.661136800 +0800
+++ grlib-gpl-2024.4-b4295\lib\techmap\unisim\ddr_unisim.vhd 2025-02-01 00:23:27.915784200 +0800
@@ -106,7 +106,7 @@
begin
KU : if (tech = kintexu) or (tech = virtexup) generate
- U0 : IDDRE1 generic map( IS_CB_INVERTED => '1')
+ U0 : IDDRE1 generic map( IS_CB_INVERTED => '0')
Port map(Q1 => Q1, Q2 => Q2, C => C1, CB => C1, D => D, R => R);
end generate;
@@ -328,6 +328,22 @@
architecture rtl of unisim_oddr_reg is
attribute BOX_TYPE : string;
+ component ODDRE1
+ generic (
+ IS_C_INVERTED : bit := '0'; -- Optional inversion for C
+ IS_D1_INVERTED : bit := '0'; -- Unsupported, do not use
+ IS_D2_INVERTED : bit := '0'; -- Unsupported, do not use
+ SIM_DEVICE : string := "ULTRASCALE_PLUS"; -- Set the device version for simulation functionality (ULTRASCALE,
+ -- ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
+ SRVAL : bit := '0'); -- Initializes the ODDRE1 Flip-Flops to the specified value ('0', '1')
+ port (
+ Q : out std_logic;
+ C : in std_logic;
+ D1 : in std_logic;
+ D2 : in std_logic;
+ SR : in std_logic);
+ end component;
+ attribute BOX_TYPE of ODDRE1 : component is "PRIMITIVE";
component ODDR
generic
@@ -391,6 +407,11 @@
begin
+ KU : if (tech = kintexu) or (tech = virtexup) generate
+ U0 : ODDRE1 generic map(SRVAL => '0', IS_C_INVERTED => '0', IS_D1_INVERTED => '0', IS_D2_INVERTED => '0', SIM_DEVICE => "ULTRASCALE_PLUS")
+ port map(Q => Q, C => C1, D1 => D1, D2 => D2, SR => R);
+ end generate;
+
V7 : if (tech = virtex7) or (tech = kintex7) or (tech = artix7) generate
U0 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE")
port map(
```
---
### Author:  [@joaquin.espana](https://discourse.grlib.community/u/joaquin.espana)
#### Post date: [1 April 2025 10:19 UTC](https://discourse.grlib.community/t/can-rgmii-ip-be-used-for-xilinx-ultrascale-technology/464/3 "2025-04-01T10:19:15Z")
Hi WEI,
Thanks for the patch! I will look into adding this to the Ultrascale techmap implementation. I’d say your change looks good though, but we need to test this on our side to be able to confirm it.
Regards,
Joaquin
---
### Author:  [@joaquin.espana](https://discourse.grlib.community/u/joaquin.espana)
#### Post date: [24 June 2025 14:59 UTC](https://discourse.grlib.community/t/can-rgmii-ip-be-used-for-xilinx-ultrascale-technology/464/4 "2025-06-24T14:59:20Z")
Hi WEI,
This has now been integrated in GRLIB and will be part of the June release. Your suggestion to include the missing ODDRE1 component for Ultrascale was definitely correct and is now in place. However, changing the generic IS\_CB\_INVERTED in IDDRE1 from ‘1’ to ‘0’ was not included. In our tests, that would mean that only ‘even’ data are sampled (and twice, Q2 = Q1 shifted). Did you fully validate this change on your side?
Regards,
Joaquin
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### Author:  [@WEI](https://discourse.grlib.community/u/WEI)
#### Post date: [26 June 2025 01:34 UTC](https://discourse.grlib.community/t/can-rgmii-ip-be-used-for-xilinx-ultrascale-technology/464/5 "2025-06-26T01:34:07Z")
I don’t quite remember the considerations at that time, it works on real hardware, but it has not been fully confirmed through stress testing and EDA simulation.
Actually, I removed the change to IDDRE1 later.