# NOEL-V

**URL:** https://discourse.grlib.community/c/noel-v/8.md

[Latest](https://discourse.grlib.community/latest.md) · [Categories](https://discourse.grlib.community/categories.md)

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## [About the NOEL-V category](https://discourse.grlib.community/t/about-the-noel-v-category/20)

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**Author:** [@daniel](https://discourse.grlib.community/u/daniel)\
**Replies:** 0

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Topics about the NOEL-V processor, the IP, SoCs, configurations, RISC-V standards, extensions, porting to FPGA boards, on-chip bus interfaces, caches, architecture, etc.

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## [Custom AHB Slave Integration in NOEL-V Generic (GRLIB GPL 2025.2) ](https://discourse.grlib.community/t/custom-ahb-slave-integration-in-noel-v-generic-grlib-gpl-2025-2/566)

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**Author:** [@THEDARKHORSE](https://discourse.grlib.community/u/THEDARKHORSE)\
**Replies:** 2\
**Last updated:** [26 August 2026 05:56 UTC](https://discourse.grlib.community/t/custom-ahb-slave-integration-in-noel-v-generic-grlib-gpl-2025-2/566 "2026-08-26T05:56:30Z")

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Hello, I am integrating a custom AHB slave into the NOEL-V Generic reference design (GRLIB GPL 2025.2) targeting a Xilinx ZCU102 board. The custom slave is instantiated in noelvcore.vhd with: hindex = 9 haddr = 1…

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## [Troubleshooting VCU118 design issues in 2026.2](https://discourse.grlib.community/t/troubleshooting-vcu118-design-issues-in-2026-2/579)

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**Author:** [@MarcSB](https://discourse.grlib.community/u/MarcSB)\
**Replies:** 3\
**Last updated:** [10 August 2026 08:51 UTC](https://discourse.grlib.community/t/troubleshooting-vcu118-design-issues-in-2026-2/579 "2026-08-10T08:51:44Z")

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Hello everyone, We are currently experiencing several issues with the new VCU118 design provided in the 2026.2 release and were wondering if anyone has encountered something similar. For context, we have a working desi…

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## [Issues with 2026.2 on Digilent Arty-A7](https://discourse.grlib.community/t/issues-with-2026-2-on-digilent-arty-a7/584)

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**Author:** [@robamu](https://discourse.grlib.community/u/robamu)\
**Replies:** 1\
**Last updated:** [4 August 2026 11:11 UTC](https://discourse.grlib.community/t/issues-with-2026-2-on-digilent-arty-a7/584 "2026-08-04T11:11:08Z")

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Hello, First of all, thanks a lot for providing the open-source Noel-V design! It is a great thing this exists and I learnt a lot while using it. I am currently trying some experiment of running Rust on a Noel-V using t…

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## [Noelv risc-v vector extension](https://discourse.grlib.community/t/noelv-risc-v-vector-extension/574)

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**Author:** [@laurentiuduca](https://discourse.grlib.community/u/laurentiuduca)\
**Replies:** 0\
**Last updated:** [26 June 2026 10:35 UTC](https://discourse.grlib.community/t/noelv-risc-v-vector-extension/574 "2026-06-26T10:35:57Z")

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Hello grlib community, I am an open source enthusiast with various projects on github. I gladly found the paper “Extending the NOEL-V Platform with a RISC-V Vector Processor for Space Applications”, Mascio, S. D., Menic…

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## [NOEL-V CoreMark](https://discourse.grlib.community/t/noel-v-coremark/549)

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**Author:** [@Based](https://discourse.grlib.community/u/Based)\
**Replies:** 2\
**Last updated:** [2 March 2026 17:57 UTC](https://discourse.grlib.community/t/noel-v-coremark/549 "2026-03-02T17:57:07Z")

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Is it really true that NOEL-V is able to reach up to 4.69 CoreMark/MHz? After series of tests, we’ve measured the best score we could with the GRLIB Release 2025.1-b4296. 10 iterations were running for almost 12 seconds…

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## [Debugging NOEL-V Over a JTAG Tunnel with OpenOCD](https://discourse.grlib.community/t/debugging-noel-v-over-a-jtag-tunnel-with-openocd/552)

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**Author:** [@WEI](https://discourse.grlib.community/u/WEI)\
**Replies:** 1\
**Last updated:** [28 January 2026 13:36 UTC](https://discourse.grlib.community/t/debugging-noel-v-over-a-jtag-tunnel-with-openocd/552 "2026-01-28T13:36:18Z")

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Hello, To reuse the same JTAG cable for both FPGA configuration and NOEL debugging, I chose the AHBJTAGRV with Xilinx FPGA TAP as the debugging link. mon\_ocd : ahbjtagrv generic map (tech =\> CFG\_AHB\_JTAG\_TEK, dtm\_sel =\>…

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## [Help debbuging within iunv.vhd](https://discourse.grlib.community/t/help-debbuging-within-iunv-vhd/546)

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**Author:** [@Based](https://discourse.grlib.community/u/Based)\
**Replies:** 4\
**Last updated:** [28 November 2025 10:26 UTC](https://discourse.grlib.community/t/help-debbuging-within-iunv-vhd/546 "2025-11-28T10:26:36Z")

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Hi to everyone Currently trying to simulate a NOEL-V release 2025.1-b4296 core with Modelsim. It works for a good portion of simulation, but then break with the following error: Failure: X in data going to cache And t…

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## [Handling interrupts in NOEL](https://discourse.grlib.community/t/handling-interrupts-in-noel/544)

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**Author:** [@Based](https://discourse.grlib.community/u/Based)\
**Replies:** 2\
**Last updated:** [14 October 2025 18:01 UTC](https://discourse.grlib.community/t/handling-interrupts-in-noel/544 "2025-10-14T18:01:20Z")

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I can’t figure how exactly does NOEL handle interrupts. According to The RISC-V Instruction Set Manual, all I need to do to enable interrupts is to set mstatus.MIE bit, enable them in mie csr register and write trap han…

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## [Plug & Play issue of NOEL-V SoC for GRLIB 2025.2](https://discourse.grlib.community/t/plug-play-issue-of-noel-v-soc-for-grlib-2025-2/540)

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**Author:** [@jyk](https://discourse.grlib.community/u/jyk)\
**Replies:** 6\
**Last updated:** [24 September 2025 12:13 UTC](https://discourse.grlib.community/t/plug-play-issue-of-noel-v-soc-for-grlib-2025-2/540 "2025-09-24T12:13:52Z")

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I am currently using NOEL-V processor, But I am facing the issue of GRMON cannot detect when integrating some other components to the AHB bus. Initially, I utilised the design template noelv-xilinx-zcu102 and successful…

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## [Issues when updating to GRLIB GPL 2025.2](https://discourse.grlib.community/t/issues-when-updating-to-grlib-gpl-2025-2/524)

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**Author:** [@MarcSB](https://discourse.grlib.community/u/MarcSB)\
**Replies:** 4\
**Last updated:** [27 August 2025 15:45 UTC](https://discourse.grlib.community/t/issues-when-updating-to-grlib-gpl-2025-2/524 "2025-08-27T15:45:54Z")

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Hello all, We recently upgraded our NOEL-V system from GPL 2023.4 to 2025.2, running on a Xilinx VCU118 FPGA. After the update, our ADA port (developed by @GuillermoVidal) stopped working. We updated all addresses as pe…

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## [NOELV L1 cache, replacement policy issue](https://discourse.grlib.community/t/noelv-l1-cache-replacement-policy-issue/517)

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**Author:** [@Lucas\_Elsys\_Design](https://discourse.grlib.community/u/Lucas_Elsys_Design)\
**Replies:** 4\
**Last updated:** [23 July 2025 08:44 UTC](https://discourse.grlib.community/t/noelv-l1-cache-replacement-policy-issue/517 "2025-07-23T08:44:13Z")

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Hello, I am currently using NOELV CPU (64 bits), and its L1 cache. From the specification, I understand that LRU replacement should be used when, for a given L1 cache set, all the 4 ways are in use (and a new line is to…

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## [L2C lite cache IP, PLRU replacement issue](https://discourse.grlib.community/t/l2c-lite-cache-ip-plru-replacement-issue/516)

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**Author:** [@Lucas\_Elsys\_Design](https://discourse.grlib.community/u/Lucas_Elsys_Design)\
**Replies:** 2\
**Last updated:** [4 July 2025 09:32 UTC](https://discourse.grlib.community/t/l2c-lite-cache-ip-plru-replacement-issue/516 "2025-07-04T09:32:42Z")

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Hello, I am experiencing some issues with L2C lite IP, in a design where NOELV CPU (64 bits) is used. In fact, I noticed that when I select PLRU replacement mode, only 2 ways out of 4 are used (I configured L2C lite IP …

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## [Design Compiler and Formality tool of synopsys showing error in RTL code](https://discourse.grlib.community/t/design-compiler-and-formality-tool-of-synopsys-showing-error-in-rtl-code/502)

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**Author:** [@Chiragkumar](https://discourse.grlib.community/u/Chiragkumar)\
**Replies:** 2\
**Last updated:** [23 April 2025 12:10 UTC](https://discourse.grlib.community/t/design-compiler-and-formality-tool-of-synopsys-showing-error-in-rtl-code/502 "2025-04-23T12:10:33Z")

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For Microcontroller Version with 32 bits Following lines showing error in code during synthesis or/and formality. File Name : nvsupport.vhd - LINE NO. 8438 to 8445 ( Reason : wdata size 32 bit and function try to acc…

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## [NOEL-V XLEN 64 bits with AHB 32 bits](https://discourse.grlib.community/t/noel-v-xlen-64-bits-with-ahb-32-bits/498)

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**Author:** [@Lucas\_Elsys\_Design](https://discourse.grlib.community/u/Lucas_Elsys_Design)\
**Replies:** 2\
**Last updated:** [17 April 2025 13:23 UTC](https://discourse.grlib.community/t/noel-v-xlen-64-bits-with-ahb-32-bits/498 "2025-04-17T13:23:18Z")

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Hello, Into our design we have configure NOEL-V processor with XLEN = 64 (configuration CFG\_NOELV\_XLEN = 64) We would like to have the internal AHB size to 32 bits length (configuration of CFG\_AHBDW=64) In this config…

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## [Large Physical Addressing](https://discourse.grlib.community/t/large-physical-addressing/446)

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**Author:** [@WEI](https://discourse.grlib.community/u/WEI)\
**Replies:** 1\
**Last updated:** [1 April 2025 10:22 UTC](https://discourse.grlib.community/t/large-physical-addressing/446 "2025-04-01T10:22:52Z")

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Hi, I see that leon-linux-5.10-1.8 has added support for 36-bit physical addresses. Will new LEON hardware be included in the next GRLIB ? Also, does NOEL have a corresponding plan ?

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## [NOEL-V on Pynq-Z2](https://discourse.grlib.community/t/noel-v-on-pynq-z2/457)

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**Author:** [@digi9](https://discourse.grlib.community/u/digi9)\
**Replies:** 1\
**Last updated:** [1 April 2025 10:21 UTC](https://discourse.grlib.community/t/noel-v-on-pynq-z2/457 "2025-04-01T10:21:03Z")

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Hello, I am trying to port NOEL-V on Pynq-Z2 (using Linux Debian PC). However, I am having trouble following the GRLIB guides as to what steps I need to follow to get this to work. I am under the impression that for boa…

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## [Logic Equivalence Check using formality tool having fatal error for cctrlnv.vhd and cpucorenv.vhd](https://discourse.grlib.community/t/logic-equivalence-check-using-formality-tool-having-fatal-error-for-cctrlnv-vhd-and-cpucorenv-vhd/488)

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**Author:** [@Chiragkumar](https://discourse.grlib.community/u/Chiragkumar)\
**Replies:** 1\
**Last updated:** [1 April 2025 10:16 UTC](https://discourse.grlib.community/t/logic-equivalence-check-using-formality-tool-having-fatal-error-for-cctrlnv-vhd-and-cpucorenv-vhd/488 "2025-04-01T10:16:41Z")

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For Release 2024.4-b4295 I am performing equivalency check of RTL and netlist (generated using Design Compiler) using formality tool of Synopsys. cctrlnv.vhd and cpucorenv.vhd file shows fatal error during execution o…

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## [Multiple warnings for NOEL-V 32-bit](https://discourse.grlib.community/t/multiple-warnings-for-noel-v-32-bit/483)

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**Author:** [@rcardenas](https://discourse.grlib.community/u/rcardenas)\
**Replies:** 2\
**Last updated:** [10 March 2025 07:34 UTC](https://discourse.grlib.community/t/multiple-warnings-for-noel-v-32-bit/483 "2025-03-10T07:34:16Z")

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We are working on NOEL-V designs for an VCU-118 FPGA. Currently, we are able to implement, simulate, and program the FPGA with a basic 64-bit version of NOEL-V. However, when exploring the same design but using the 32-bi…

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## [Please help to simulate noelv-generic](https://discourse.grlib.community/t/please-help-to-simulate-noelv-generic/448)

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**Author:** [@laurentiuduca](https://discourse.grlib.community/u/laurentiuduca)\
**Replies:** 9\
**Last updated:** [21 January 2025 14:48 UTC](https://discourse.grlib.community/t/please-help-to-simulate-noelv-generic/448 "2025-01-21T14:48:59Z")

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Hello, I am trying to compile noel-v systest using ‘make soft’ with ncc-1.0.4-gcc (the single compiler for noel-v that i’ve found on the gasiler.com site) i get the following error laur@laurPC-100:noelv-generic$ make…

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## [Simulation problem with stdlib](https://discourse.grlib.community/t/simulation-problem-with-stdlib/172)

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**Author:** [@mehdy](https://discourse.grlib.community/u/mehdy)\
**Replies:** 1\
**Last updated:** [15 November 2024 23:04 UTC](https://discourse.grlib.community/t/simulation-problem-with-stdlib/172 "2024-11-15T23:04:52Z")

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Hello, I want to implement some programs using the stdlib library, and then simulating it using modelsim. It compil just fine with the gaisler toolchain, but when i run the simulation, malloc() always return NULL and ra…

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## [Unable to implement i2cmst in NOEL-V](https://discourse.grlib.community/t/unable-to-implement-i2cmst-in-noel-v/430)

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**Author:** [@steewBSD](https://discourse.grlib.community/u/steewBSD)\
**Replies:** 1\
**Last updated:** [5 August 2024 08:27 UTC](https://discourse.grlib.community/t/unable-to-implement-i2cmst-in-noel-v/430 "2024-08-05T08:27:30Z")

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Hello. After adding some code by hand and following the example code for i2cmst in the GRLIB IP core manual, I haven’t been unable to get the i2cmst peripheral to show in GRMON for the vcu118 FPGA. i2c\_ex : if (CFG\_I2C\_…

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## [NOEL-V VC707 Issues](https://discourse.grlib.community/t/noel-v-vc707-issues/59)

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**Author:** [@Justin](https://discourse.grlib.community/u/Justin)\
**Replies:** 7\
**Last updated:** [28 May 2024 14:31 UTC](https://discourse.grlib.community/t/noel-v-vc707-issues/59 "2024-05-28T14:31:18Z")

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Hello, First just wanted to say thank you to putting this library and RTL out on a GPL License! I’m a student and my research is in RISC-V, and it’s hard to find 64-bit RISC-V IP designs to use for research. On to my q…

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## [FPU disabled on VCU-118](https://discourse.grlib.community/t/fpu-disabled-on-vcu-118/407)

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**Author:** [@steewBSD](https://discourse.grlib.community/u/steewBSD)\
**Replies:** 7\
**Last updated:** [28 April 2024 07:31 UTC](https://discourse.grlib.community/t/fpu-disabled-on-vcu-118/407 "2024-04-28T07:31:02Z")

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Greetings. I have been trying to synthesize NOEL-V in the Xilinx VCU-118. I have reached a functional implementation, with GRMON successfully reporting the system information. Unfortunately, I have not been able to get …

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## [Linux 6.3.0 Kernel panic](https://discourse.grlib.community/t/linux-6-3-0-kernel-panic/383)

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**Author:** [@WEI](https://discourse.grlib.community/u/WEI)\
**Replies:** 2\
**Last updated:** [22 January 2024 13:39 UTC](https://discourse.grlib.community/t/linux-6-3-0-kernel-panic/383 "2024-01-22T13:39:19Z")

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I try the resulting image of gaisler-buildroot-2023.02-1.0.tar.bz2, get an error: Linux version 6.3.0 (riscv64-gaisler-linux-gnu-gcc.br\_real (Buildroot 2023.02.4-gaisler1.0) 12.3.0, GNU ld (GNU Binutils) 2.38) #2 SMP We…

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## [NoelV simulation on Vivado fails because of segmentation error](https://discourse.grlib.community/t/noelv-simulation-on-vivado-fails-because-of-segmentation-error/373)

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**Author:** [@Vittorio](https://discourse.grlib.community/u/Vittorio)\
**Replies:** 0\
**Last updated:** [20 October 2023 07:29 UTC](https://discourse.grlib.community/t/noelv-simulation-on-vivado-fails-because-of-segmentation-error/373 "2023-10-20T07:29:12Z")

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Hi community! I’m having an issue simulating the Noel V processor on vivado tools. Starting from grlib i used the make file in order to configure and simulate the processor. The OS is Ubuntu 22.04.2 and vivado 2022.1. On…

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## [Monitor the internal signal with the ILA](https://discourse.grlib.community/t/monitor-the-internal-signal-with-the-ila/360)

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**Author:** [@ciaociao](https://discourse.grlib.community/u/ciaociao)\
**Replies:** 4\
**Last updated:** [12 September 2023 15:24 UTC](https://discourse.grlib.community/t/monitor-the-internal-signal-with-the-ila/360 "2023-09-12T15:24:24Z")

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Hello, may I ask if it’s possible to add the Integrated Logic Analyzer (ILA) to the NOEL-V SoC design to monitor the internal signals? I tried adding the ILA or VIO to the NOEL-V design, which can be synthesized, but I…

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## [NOELV Arty-A7 not connecting to GRMON](https://discourse.grlib.community/t/noelv-arty-a7-not-connecting-to-grmon/353)

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**Author:** [@nicoladgg](https://discourse.grlib.community/u/nicoladgg)\
**Replies:** 4\
**Last updated:** [9 August 2023 15:00 UTC](https://discourse.grlib.community/t/noelv-arty-a7-not-connecting-to-grmon/353 "2023-08-09T15:00:08Z")

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Hi everyone, I’m trying to use the noelv core on an Arty A7 FPGA using the bitstreams given. I haven’t been able to connect using GRMON to any of the bitstreams, starting from the beginning of 2022 up to the last ones g…

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## [Help simulating NOEL-V with GHDL](https://discourse.grlib.community/t/help-simulating-noel-v-with-ghdl/69)

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**Author:** [@MarcSB](https://discourse.grlib.community/u/MarcSB)\
**Replies:** 17\
**Last updated:** [7 June 2023 09:30 UTC](https://discourse.grlib.community/t/help-simulating-noel-v-with-ghdl/69 "2023-06-07T09:30:09Z")

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Hello, I’m doing a master project with the NOEL-V, I was hoping somebody could help me resolve some doubts. I don’t have an FPGA at the moment, so I’m trying to do a simulation using GHDL. I have changed the TECHLIBS an…

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## [NOEL-V/ IP MIG 7 Series on ARTY-A7](https://discourse.grlib.community/t/noel-v-ip-mig-7-series-on-arty-a7/341)

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**Author:** [@Marte](https://discourse.grlib.community/u/Marte)\
**Replies:** 1\
**Last updated:** [29 May 2023 14:00 UTC](https://discourse.grlib.community/t/noel-v-ip-mig-7-series-on-arty-a7/341 "2023-05-29T14:00:54Z")

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Dear, I´m trying synthesis the project “noelv-digilent-arty-a7” but I get a error because the difference of MIG 7 IP. The original version in the grlib is from Vivado 2018.1 (4.1), but the recent Vivado versions use the…

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